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ST
Sitronix
1. INTRODUCTION
ST7628
65K Color Dot Matrix LCD Controller/Driver
The ST7628 is a driver & controller LSI for 65K color graphic dot-matrix liquid crystal display systems. It generates 294 Segment and 70 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI) or 8-bit/16-bit parallel display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver Output Circuits
294 Segment Outputs / 70 Common Outputs
3-line (9-bits) serial interface
On-chip Low Power Analog Circuit
On-chip Oscillator Circuit On-chip Voltage Converter (x2, x3, x4, x5, x6, x7, X8) with internal booster capacitors. Extremely Few Outsider Components. (Required outsider components: Three Capacitors) On-chip Voltage Regulator On-chip Electronic Contrast Control Function Voltage Follower (LCD bias: 1/5~1/12)
Applicable Duty Ratios
Various Partial Display Partial Window Moving & Data Scrolling
Gray-Scale Display
4FRC & 31 PWM function circuit to display 64 gray-scale display Support 8 color mode (Idle mode)
On-chip Display Data RAM
Capacity: 98 x 70 x 16 =109,760 bits
Operating Voltage Range
Supply Digital Voltage (VDD): 1.65 to 3.0V Supply Analog Voltage (VDD2, VDD3, VDD4, VDD5): 2.4 to 3.3V LCD Driving Voltage (VOP = V0 - VSS): Max to 18V
Color support by Interface
256 color mode (via LUT) 4K color mode (via LUT) 65K color mode Truncated 262K color mode Truncated 16M color mode
LCD Driving Voltage (OTP)
Contrast Adjustment Value is stored in the Built-In OTP-ROM for better display quality.
Microprocessor Interface
8/16-bit parallel bi-directional interface with 6800-series or 8080-series 4-line serial interface
LCD Driving setting suggestion
LCD Driving Voltage (VOP = 11.72V), BIAS=1/8.
Package Type
Application for COG
ST7628
6800 , 8080 ,4-Line , 3-Line interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. Ver 1.4 1/213 2008/08
ST7628
3. ST7628 Pad Arrangement (COG)
Chip Size :
10070 um x 780 um
Bump Pitch :
PAD 1~2, 3~14 pitch=27um(min, com/seg)
152 COM5
137 VSS 136 VgIn 135 VgIn
PAD 138~149, 150~517 pitch=27um(min, com/seg) PAD 2~3, 149~150 pitch=28.79um(min, com/seg) PAD 15 ~ 28, 29~137 pitch=80um (I/O) PAD 28~29 pitch = 79.72um(I/O)
184 COM69 188 SEG0
130 VgIn 129 VgIn 128 VgS 127 VgOut 126 VgOout 125 XV0In 124 XV0In 123 XV0In 122 XV0In 121 XV0S 120 XV0Out 119 XV0Out 118 V0Out 117 V0Out 116 V0S 115 V0In 114 V0In 113 V0In 112 V0In 111 VREF 110 Vm 109 VDD2
Bump Size :
PAD 1 ~ 14 , PAD 138 ~ 517 Bump width=14um(min, com/seg) Bump space=13um(min, com/seg) Bump length=128um(min, com/seg) Bump area=1800um^2(com/seg) PAD 15 ~28, 29~137 Bump width=65um(I/O) Bump space=15um(I/O) Bump length=63um(I/O) Bump area=4095um^2 PAD 28~29 Bump width=65um(I/O) Bump space=14.72um(I/O) Bump length=63um(I/O) Bump area=4095um^2
100 VDD2 99 98 97 96 95 94 93 92 91 90 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD4 VDD4
89 VDD3 88 VDD3 87 VSS4 86 VSS4 85 VSS2 84 VSS2 83 VSS2 82 VSS2
X Y (0,0)
76 VSS2 75 VSS2 74 VSS2 73 VSS 72 VSS 71 VSS 70 VSS 69 VSS1 68 VSS1 67 VDD 66 VDD 65 VDD 64 VDD 63 VDD 62 VDD 61 TCAP 60 TE 59 /EXT 58 /CS 57 VDD 56 VSS 55 IF3 54 IF2 53 IF1 52 CSEL 51 RST 50 E_RD 49 VDD 48 VSS 47 D15 46 D14 45 D13 44 D12 43 D11 42 D10 41 D9 40 D8 39 D7 38 D6 37 D5 36 D4 35 D3 34 D2 33 D1 32 D0 31 RW_WR 30 A0 29 VDD 28 CLS 27 CL 26 VPP 25 VPP 24 VPP 23 VPP 22 VSS 21 dummy
Bump Height : 15 um Chip Thickness : 400 um
Alignment mark
The center of alignment mark: see bellow Table
Left L-Mark
55 15 15 57 Center 15 15
Right L-Mark
55
481 SEG293 485 COM68
57 Center
517 COM4
15 dummy
15 15
15 15
Ver 1.4
2/213
2008/08
ST7628
4. Pad Center Coordinates
35 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Ver 1.4
D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST CSEL IF1 IF2 IF3 VSS VDD /CS /EXT TE TCAP VDD VDD VDD VDD VDD VDD VSS1 VSS1 VSS
-3271.08 -299.50 -3191.08 -299.50 -3111.08 -299.50 -3031.08 -299.50 -2951.08 -299.50 -2871.08 -299.50 -2791.08 -299.50 -2711.08 -299.50 -2631.08 -299.50 -2551.08 -299.50 -2471.08 -299.50 -2391.08 -299.50 -2311.08 -299.50 -2231.08 -299.50 -2151.08 -299.50 -2071.08 -299.50 -1991.08 -299.50 -1911.08 -299.50 -1831.08 -299.50 -1751.08 -299.50 -1671.08 -299.50 -1591.08 -299.50 -1511.08 -299.50 -1431.08 -299.50 -1351.08 -299.50 -1271.08 -299.50 -1191.08 -299.50 -1111.08 -299.50 -1031.08 -299.50 -951.08 -871.08 -791.08 -711.08 -631.08 -551.08 -471.08 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50
2008/08
IC-NAME COM2 COM0 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VSS VPP VPP VPP VPP CL CLS VDD A0 RW_WR D0 D1 D2
X -4917.71 -4917.71 -4917.71 -4917.71 -4917.71 -4917.71 -4917.71 -4917.71
Y 116.94 89.94 61.15 34.15 7.15 -19.85 -46.85 -73.85
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
3/213
-4917.71 -100.85 -4917.71 -127.85 -4917.71 -154.85 -4917.71 -181.85 -4917.71 -208.85 -4917.71 -235.85 -4870.80 -299.50 -4790.80 -299.50 -4710.80 -299.50 -4630.80 -299.50 -4550.80 -299.50 -4470.80 -299.50 -4390.80 -299.50 -4310.80 -299.50 -4230.80 -299.50 -4150.80 -299.50 -4070.80 -299.50 -3990.80 -299.50 -3910.80 -299.50 -3830.80 -299.50 -3751.08 -299.50 -3671.08 -299.50 -3591.08 -299.50 -3511.08 -299.50 -3431.08 -299.50 -3351.08 -299.50
ST7628
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
Ver 1.4
VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS4 VSS4 VDD3 VDD3 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2
-391.08 -311.08 -231.08 -151.08 -71.08 8.92 88.92 168.92 248.92 328.92 408.92 488.92 568.92 648.92 728.92 808.92 888.92 968.92 1128.92
-299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50 -299.50
108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
4/213
VDD2 VDD2 Vm VREF V0in V0in V0in V0in V0s V0out V0out XV0out XV0out XV0S XV0in XV0in XV0in XV0in Vgout Vgout Vgs Vgin Vgin Vgin Vgin Vgin Vgin Vgin Vgin VSS DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
2568.92 -299.50 2648.92 -299.50 2728.92 -299.50 2808.92 -299.50 2888.92 -299.50 2968.92 -299.50 3048.92 -299.50 3128.92 -299.50 3208.92 -299.50 3288.92 -299.50 3368.92 -299.50 3448.92 -299.50 3528.92 -299.50 3608.92 -299.50 3688.92 -299.50 3768.92 -299.50 3848.92 -299.50 3928.92 -299.50 4008.92 -299.50 4088.92 -299.50 4168.92 -299.50 4248.92 -299.50 4328.92 -299.50 4408.92 -299.50 4488.92 -299.50 4568.92 -299.50 4648.92 -299.50 4728.92 -299.50 4808.92 -299.50 4888.92 -299.50 4917.71 -235.85 4917.71 -208.85 4917.71 -181.85 4917.71 -154.85 4917.71 -127.85 4917.71 -100.85 4917.71 -73.85
2008/08
1048.92 -299.50 1208.92 -299.50 1288.92 -299.50 1368.92 -299.50 1448.92 -299.50 1528.92 -299.50 1608.92 -299.50 1688.92 -299.50 1768.92 -299.50 1848.92 -299.50 1928.92 -299.50 2008.92 -299.50 2088.92 -299.50 2168.92 -299.50 2248.92 -299.50 2328.92 -299.50 2408.92 -299.50 2488.92 -299.50
ST7628
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
Ver 1.4
DUMMY DUMMY DUMMY DUMMY DUMMY COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63
4917.71 4917.71 4917.71 4917.71 4917.71 4917.71 4917.71 4938.50 4911.50 4884.50 4857.50 4830.50 4803.50 4776.50 4749.50 4722.50 4695.50 4668.50 4641.50 4614.50 4587.50 4560.50 4533.50 4506.50 4479.50 4452.50 4425.50 4398.50 4371.50 4344.50 4317.50 4290.50 4263.50 4236.50 4209.50 4182.50 4155.50
-46.85 -19.85 7.15 34.15 61.15 89.94 116.94 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71
182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218
5/213
COM65 COM67 COM69 L-Mark L-Mark L-Mark SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
4128.50 4101.50 4074.50 4038.50 4038.50 4038.50 3955.50 3928.50 3901.50 3874.50 3847.50 3820.50 3793.50 3766.50 3739.50 3712.50 3685.50 3658.50 3631.50 3604.50 3577.50 3550.50 3523.50 3496.50 3469.50 3442.50 3415.50 3388.50 3361.50 3334.50 3307.50 3280.50 3253.50 3226.50 3199.50 3172.50 3145.50
272.71 272.71 272.71 325.00 325.00 325.00 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71
2008/08
ST7628
219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
Ver 1.4
SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67
3118.50 3091.50 3064.50 3037.50 3010.50 2983.50 2956.50 2929.50 2902.50 2875.50 2848.50 2821.50 2794.50 2767.50 2740.50 2713.50 2686.50 2659.50 2632.50 2605.50 2578.50 2551.50 2524.50 2497.50 2470.50 2443.50 2416.50 2389.50 2362.50 2335.50 2308.50 2281.50 2254.50 2227.50 2200.50 2173.50 2146.50
272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71
256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292
6/213
SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104
2119.50 2092.50 2065.50 2038.50 2011.50 1984.50 1957.50 1930.50 1903.50 1876.50 1849.50 1822.50 1795.50 1768.50 1741.50 1714.50 1687.50 1660.50 1633.50 1606.50 1579.50 1552.50 1525.50 1498.50 1471.50 1444.50 1417.50 1390.50 1363.50 1336.50 1309.50 1282.50 1255.50 1228.50 1201.50 1174.50 1147.50
272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71
2008/08
ST7628
293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329
Ver 1.4
SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 SEG139 SEG140 SEG141
1120.50 1093.50 1066.50 1039.50 1012.50 985.50 958.50 931.50 904.50 877.50 850.50 823.50 796.50 769.50 742.50 715.50 688.50 661.50 634.50 607.50 580.50 553.50 526.50 499.50 472.50 445.50 418.50 391.50 364.50 337.50 310.50 283.50 256.50 229.50 202.50 175.50 148.50
272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71
330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366
7/213
SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG161 SEG162 SEG163 SEG164 SEG165 SEG166 SEG167 SEG168 SEG169 SEG170 SEG171 SEG172 SEG173 SEG174 SEG175 SEG176 SEG177 SEG178
121.50 94.50 67.50 40.50 13.50 -13.50 -40.50 -67.50 -94.50 -121.50 -148.50 -175.50 -202.50 -229.50 -256.50 -283.50 -310.50 -337.50 -364.50 -391.50 -418.50 -445.50 -472.50 -499.50 -526.50 -553.50 -580.50 -607.50 -634.50 -661.50 -688.50 -715.50 -742.50 -769.50 -796.50 -823.50 -850.50
272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71 272.71
2008/08
ST7628
367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403
Ver 1.4
SEG179 SEG180 SEG181 SEG182 SEG183 SEG184 SEG185 SEG186 SEG187 SEG188 SEG189 SEG190 SEG191 SEG192 SEG193 SEG194 SEG195 SEG196 SEG197 SEG198 SEG199 SEG200 SEG201 SEG202 SEG203 SEG204 SEG205 SEG206 SEG207 SEG208 SEG209 SEG210 SEG211 SEG212 SEG213 SEG214 SEG215
-877.50 -904.50 -931.50 -958.50 -985.50
272.71 272.71 272.71 272.71 272.71
404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440
8/213
SEG216 SEG217 SEG218 SEG219 SEG220 SEG221 SEG222 SEG223 SEG224 SEG225 SEG226 SEG227 SEG228 SEG229 SEG230 SEG231 SEG232 SEG233 SEG234 SEG235 SEG236 SEG237 SEG238 SEG239 SEG240 SEG241 SEG242 SEG243 SEG244 SEG245 SEG246 SEG247 SEG248 SEG249 SEG250 SEG251 SEG252
-1876.50 272.71 -1903.50 272.71 -1930.50 272.71 -1957.50 272.71 -1984.50 272.71 -2011.50 272.71 -2038.50 272.71 -2065.50 272.71 -2092.50 272.71 -2119.50 272.71 -2146.50 272.71 -2173.50 272.71 -2200.50 272.71 -2227.50 272.71 -2254.50 272.71 -2281.50 272.71 -2308.50 272.71 -2335.50 272.71 -2362.50 272.71 -2389.50 272.71 -2416.50 272.71 -2443.50 272.71 -2470.50 272.71 -2497.50 272.71 -2524.50 272.71 -2551.50 272.71 -2578.50 272.71 -2605.50 272.71 -2632.50 272.71 -2659.50 272.71 -2686.50 272.71 -2713.50 272.71 -2740.50 272.71 -2767.50 272.71 -2794.50 272.71 -2821.50 272.71 -2848.50 272.71
2008/08
-1012.50 272.71 -1039.50 272.71 -1066.50 272.71 -1093.50 272.71 -1120.50 -1147.50 -1174.50 272.71 272.71 272.71
-1201.50 272.71 -1228.50 272.71 -1255.50 272.71 -1282.50 272.71 -1309.50 272.71 -1336.50 272.71 -1363.50 272.71 -1390.50 272.71 -1417.50 272.71 -1444.50 272.71 -1471.50 272.71 -1498.50 272.71 -1525.50 272.71 -1552.50 272.71 -1579.50 272.71 -1606.50 272.71 -1633.50 272.71 -1660.50 272.71 -1687.50 272.71 -1714.50 272.71 -1741.50 272.71 -1768.50 272.71 -1795.50 272.71 -1822.50 272.71 -1849.50 272.71
ST7628
441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477
Ver 1.4
SEG253 SEG254 SEG255 SEG256 SEG257 SEG258 SEG259 SEG260 SEG261 SEG262 SEG263 SEG264 SEG265 SEG266 SEG267 SEG268 SEG269 SEG270 SEG271 SEG272 SEG273 SEG274 SEG275 SEG276 SEG277 SEG278 SEG279 SEG280 SEG281 SEG282 SEG283 SEG284 SEG285 SEG286 SEG287 SEG288 SEG289
-2875.50 272.71 -2902.50 272.71 -2929.50 272.71 -2956.50 272.71 -2983.50 272.71 -3010.50 272.71 -3037.50 272.71 -3064.50 272.71 -3091.50 272.71 -3118.50 272.71 -3145.50 272.71 -3172.50 272.71 -3199.50 272.71 -3226.50 272.71 -3253.50 272.71 -3280.50 272.71 -3307.50 272.71 -3334.50 272.71 -3361.50 272.71 -3388.50 272.71 -3415.50 272.71 -3442.50 272.71 -3469.50 272.71 -3496.50 272.71 -3523.50 272.71 -3550.50 272.71 -3577.50 272.71 -3604.50 272.71 -3631.50 272.71 -3658.50 272.71 -3685.50 272.71 -3712.50 272.71 -3739.50 272.71 -3766.50 272.71 -3793.50 272.71 -3820.50 272.71 -3847.50 272.71
478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514
9/213
SEG290 SEG291 SEG292 SEG293 L-Mark L-Mark L-Mark COM68 COM66 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10
-3874.50 272.71 -3901.50 272.71 -3928.50 272.71 -3955.50 272.71 -4038.50 325.00 -4038.50 325.00 -4038.50 325.00 -4074.50 272.71 -4101.50 272.71 -4128.50 272.71 -4155.50 272.71 -4182.50 272.71 -4209.50 272.71 -4236.50 272.71 -4263.50 272.71 -4290.50 272.71 -4317.50 272.71 -4344.50 272.71 -4371.50 272.71 -4398.50 272.71 -4425.50 272.71 -4452.50 272.71 -4479.50 272.71 -4506.50 272.71 -4533.50 272.71 -4560.50 272.71 -4587.50 272.71 -4614.50 272.71 -4641.50 272.71 -4668.50 272.71 -4695.50 272.71 -4722.50 272.71 -4749.50 272.71 -4776.50 272.71 -4803.50 272.71 -4830.50 272.71 -4857.50 272.71
2008/08
ST7628
515 516 517 COM8 COM6 COM4 -4884.50 272.71 -4911.50 272.71 -4938.50 272.71
Ver 1.4
10/213
2008/08
ST7628
5. BLOCK DIAGRAM
Ver 1.4
11/213
2008/08
ST7628
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Name
VDD VDD2 VDD3 VDD4 VDD5 VSS VSS1 VSS2 VSS4
I/O
Supply Supply Supply Supply Supply Supply Supply Supply Supply
Description
Power supply for logic circuit (Digital VDD 1.65V~3.0V) Power supply for Booster Circuit (Analog VDD 2.4V~3.3V) Power supply for LCD. (Analog VDD 2.4V~3.3V) Power supply for LCD. (Analog VDD 2.4V~3.3V) Power supply for LCD. (Analog VDD 2.4V~3.3V) Ground for logic circuit. Ground system should be connected together. Ground for OSC circuit. Ground system should be connected together. Ground for Booster Circuit. Ground system should be connected together. Ground for LCD. Ground system should be connected together.
6.2 LCD Power Supply Pins
Name I/O
Positive LCD driver supply voltages. V0OUT V0IN V0S I/O V0OUT is the output voltage of V0 generated by ST7628. V0IN is the input pin of power supply to generate V0 voltage for LCD. V0S is the input pin of power supply to sense the V0 voltage. V0OUT V0IN & V0S should be connected together. Negative LCD driver supply voltages. XV0OUT XV0IN XV0S I/O XV0OUT is the output voltage of XV0 generated by ST7628. XV0IN is the input pin of power supply to generate XV0 voltage for LCD. XV0S is the input pin of power supply to sense the XV0 voltage. XV0OUT XV0IN & XV0S should be connected together. Bias LCD driver supply voltages. VgOUT is the output voltage of Vg generated by ST7628. VgIN is the input pin of power supply to generate Vg voltage for LCD. VgS is the input pin of power supply to sense the Vg voltage. VgOUT VgIN & VgS should be connected together. VgOUT VgIN I/O VgS Vm Vm is the I/O pin of LCD bias supply voltage Voltages should have the following relationship; V0 Vg Vm VSS XV0 0.7V< Vm< VDDA-0.7V and 1.8V < Vg < 2xVDDA. When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias Vg (2/N) x V0 Vm (1/N) x V0 NOTE: N = 5 to 12
Description
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6.3 SYSTEM CONTROL
Name
CLS CL CSEL TCAP VREF VPP
I/O
Reserved for testing only. I Please fix this pin to VDD. I/O I I/O O I successfully.
Description
Reserved for testing only. Leave this pin open. This PIN should connect to VDD. Test pin. Left it opens. Reference voltage output for monitor only. Left it opened. When writing OTP, it needs external power supply voltage 7.5V~7.75V (>4mA) input to write
6.4 MICROPROCESSOR INTERFACE
Name
RST
I/O
I
Description
Reset input pin, when RST is "L", initialization is executed. Parallel / Serial data input select input
IF3 H H H IF[3:1] I H L L Note:
IF2 H H L L H H
IF1 H L H L H L
MPU interface type 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 8-bit serial (4 line) 9-bit serial (3 line)
1. When fixing IF2=H & IF1=L, IF3 can be defined as parallel/Serial selection pin. IF3=H: Parallel interface(80 8-bit); IF3=L:Serial interface(3-line) 2. Refer to Table 7.1.1. for detail interface connections. Chip select input pins /CS I Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15 become high impedance. Register select input pin A0 = "H": D0 to D15 or SI are display data A0 I A0 = "L": D0 to D15 or SI are control command In 3-line/4-line interface this pad will be used for SCL function
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Read / Write execution control pin MPU type RW_WR Description Read / Write control input pin 6800-series RW_WR I RW RW = "H" : read RW = "L" : write Write enable clock input pin 8080-series /WR The data on D0 to D15 are latched at the rising edge of the /WR signal. When in the serial interface, connect it to VSS or VDD. Read / Write execution control pin MPU Type E_RD Enable clock pin: Write status: The data on D0 to D15 are latched at the 6800-series E_RD I E falling edge of the E signal. Read status: The data on D0 to D15 are latched at the rising edge of the E signal. Read enable clock input pin 8080-series /RD The data on D0 to D15 are latched at the falling edge of the /WR signal. When in the serial interface, connect it to VSS or VDD. They connect to the standard 8-bit or 16 bit MPU bus via the 8/16 -bit bi-directional bus. When the following interface is selected and the /CS pin is high, the following pins become high impedance. D15 to D0 I/O 1. 2. 3. 4. SI I It is used by "D0" pad , See Table 7.1.1 SCL is used to input serial clock when the serial interface is selected. SCL I The data is converted in the rising edge. (3 line and 4 line) It is used by "A0" pad , See Table 7.1.1 TE O Tearing effect output. Instruction selection Pin. There is a pull-high resistor between /EXT & VDD in ST7628. /EXT I When using normal instruction table, please let it open. When using extension instruction table, please add an external VSS on /EXT. In 8-bit parallel: D15-D8 pins are in the state of high impedance should connect to VDD. In 3-line/4-line interface D0 pad will be used for SI function In 4-line interface D1 pad will be used for A0 function In Serial interface: Unused pins are in the state of high impedance should connect to VDD. Description
SI is used to input serial data when the serial interface is selected.(3 line and 4 line)
Note: 1. All of the microprocessor interface pin should not be floating on any operations. 2. Unused pins should connect to VDD(supply digital voltage) Ver 1.4 14/213 2008/08
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6.5 LCD DRIVER OUTPUTS
Name I/O LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Segment driver output voltage Display data SEG0 to SEG293 O H H L L Sleep-In mode H L H L Vg VSS VSS Vg VSS VSS Vg Vg VSS VSS M (Internal) Normal display Reverse display Description
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver.
COM0 to COM69 O
Scan data H H L L
M (Internal) H L H L
Common driver output voltage XV0 V0 Vm Vm VSS
Sleep-In mode
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ST7628 I/O PIN ITO Resister Limitation Pin Name VDD, VDD2~VDD5, VSS,VSS1,VSS2,VSS4, SI (In serial interface is D0) V0IN, V0OUT, V0S ,XV0IN, XV0OUT ,XV0S , VgIN, VgOUT ,VgS ,Vm VPP A0, E_RD, RW_WR, /CS, D0(parallel interface), D2...D15, (SCL), TE RST IF[3:1], CLS, CSEL, /EXT TCAP, CL, VREF NOTE: 1. Make sure that the ITO resistance of COM0 ~ COM69 is equal, and so is it of SEG0 ~ SEG293. These Limitations include the bottleneck of ITO layout. 2. To avoid the noise in different power system affect other power system, please separate different power source on ITO layout. 3. The V0, XV0 and Vg power circuits have output pins, input pins and a sensor input. To avoid the power noise affects the sensor of the power circuits. The trace should be separated by ITO and should be connected together by FPC. ITO Resister <100 <300 <100 <1K <10K <1K Floating
Driver Side
VDD3 VDD2 VDDx VDD
Driver Side
Separated by ITO
Separated by ITO
FPC PIN
FPC PIN
Short by FPC
FPC PIN
FPC PIN
Short by FPC
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7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
/CS pin is chip selection. The ST7628 is active when /CS=L. In serial interface mode, the internal shift register and the counter are reset when /CS=H.
7.1.1
Selecting Parallel / Serial Interface
ST7628 has six types of interface with an MPU, which are two serial and four parallel interfaces. This parallel or serial interface is determined by IF pin as shown in Table 7.1.1.
Table 7.1.1Parallel / Serial Interface Mode
I/F Mode IF3 H H H H L L IF2 H H L L H H IF1 H L H L H L I/F Description 80 serial 16-bit parallel 80 serial 8-bit parallel 68 serial 16-bit parallel 68 serial 8-bit parallel 8-bit SPI mode (4 line) 9-bit SPI mode (3 line) /CS /CS /CS /CS /CS /CS /CS A0 A0 A0 A0 A0 SCL SCL E_RD /RD /RD E E --Pin Assignment RW_WR /WR /WR R/W R/W --D15 to D8 D15 ~ D8 -D15 ~ D8 ---Used Data Bus D7 ~ D2 D7 ~ D2 D7 ~ D2 D7 ~ D2 --D1 D1 D1 D1 D1 A0 -D0 D0 D0 D0 D0 SI SI
NOTE: When these pins are set to any other combination, A0, E_RD and RW_WR inputs are disabled and D0 to D15 are to be high impedance.
7.1.2
8-bit or 16-bit Parallel Interface
The ST7628 identifies the type of the data bus signals according to the combination of A0, /RD (E) and /WR (W/R) signals, as shown in Table 7.1.2.
Table 7.1.2Parallel Data Transfer
Common A0 H H L H 6800-series R/W H H L L E /WR H H 8080-series Description /RD H H Register status read Display data read out Instruction write Display data write
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Figure 7.1Parallel Data Transfer Example Chart
Relation between Data Bus and Gradation Data The interface of ST7628 supports 256 color display, 4096 color display, 65K color display, truncated 262K color display, and truncated 16M color display. When using 256, 4096, 65K, 262K, and 16M color display; you can specify color for each of R, G, B using the palette function. Use the command for switching between these modes.
(1) 256 color input mode 1. 8-bit interface D7, D6, D5, D4, D3, D2, D1, D0: RRRGGGBB There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. 2. 16-bit interface D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXXXXXRRRGGGBB There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. "X" are ignored dummy bits. 1st writes 1st writes
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(2) 4096-color display (1-1) Type A 4096 color display 1. 8-bit interface D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGG D7, D6, D5, D4, D3, D2, D1, D0: BBBBRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB There are 3 write operations for 2 pixel data. 1st pixel data is written in the display data RAM when 2nd -write operation finishes, and 2nd pixel data is written in the display data RAM when 3rd-write operation finishes. 2. 16-bit interface D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGGBBBBXXXX There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. "X" are ignored dummy bits. (1-2) Type B 4096 color display 1. 8-bit interface D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB There are 2 write operations for 1 pixel data. 1st pixel data is written in the display data RAM when 2nd -write operation finishes. "X" are ignored dummy bits. 2. 16-bit interface D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. "X" are ignored dummy bits. (3) 65K color input mode 1. 8-bit interface D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB There are 2 write operations for 1 pixel data. 1st pixel data is written in the display data RAM when 2nd -write operation finishes. 1st writes 2nd writes 1st writes 2nd writes 1st writes 2nd writes 3rd writes
2. 16-bit interface D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB There is only 1 write operation for 1 pixel data. 1 pixel data is written in the display data RAM when 1st -write operation finishes. 1st writes
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(4) Truncated 262K color input mode 1. 8-bit interface D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXX D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGXX D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXX 1st writes 2nd writes 3rd writes
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM. "X" is dummy bit, and it is ignored for display.
2. 16-bit interface D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXXGGGGGGXX 1st writes D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXXXXXXXXXXXX 2nd writes A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
(5) Truncated 16M color input mode 1. 8-bit interface D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGGG D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBB 1st writes 2nd writes 3rd writes
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16-bit interface D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRRGGGGGGGG 1st writes D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBBXXXXXXXX 2nd writes A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
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7.1.3 8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial interface uses three pins /CS, SI and SCL for the same purpose. Data read is not available in the serial interface. Data entered must be 8 bits for each time. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation.
(1) 8-bit serial interface (4-line) When entering data (parameters): A0= HIGH at the rising edge of the 8 SCL.
th
When entering command: A0= LOW at the rising edge of the 8 SCL
th
When entering reading command:
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(2) 9-bit serial interface (3-line) When entering data (parameters): SI= HIGH at the rising edge of the 1 SCL.
st
When entering command: SI= LOW at the rising edge of the 1 SCL.
st
When entering reading command:
If /CS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again. In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register When executing the command RAMWR, set /CS to HIGH after writing the last address. The internal shift register and the counter are reset when /CS =H.
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7.1.4 8-bit and 9-bit Serial Interface Data Color Coding
8-bit serial interface (4-line) (1) R 3-bit, G 3-bit, B 2-bit, 256 colors
(2) R 4-bit, G 4-bit, B 4-bit, 4,096 colors - Type A
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(3) R 4-bit, G 4-bit, B 4-bit, 4,096 colors - Type B
(4) R 5-bit, G 6-bit, B 5-bit, 65,536 colors
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(5) R 6-bit, G 6-bit, B 6-bit, 262k colors
(6) R 8-bit, G 8-bit, B 8-bit, 16M colors
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9-bit serial interface (3-line) (1) R 3-bit, G 3-bit, B 2-bit, 256 colors
(2) R 4-bit, G 4-bit, B 4-bit, 4,096 colors - Type A
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(3) R 4-bit, G 4-bit, B 4-bit, 4,096 colors - Type B
(4) R 5-bit, G 6-bit, B 5-bit, 65,536 colors
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(5) R 6-bit, G 6-bit, B 6-bit, 262k colors
(6) R 8-bit, G 8-bit, B 8-bit, 16M colors
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7.2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7628 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Figure 7.2 illustrates these relations.
In 80-series interface mode:
MPU signal
Read Operation
A0 /WR /RD DATA Internal signals /WR /RD N Dummy D (N ) D (N +1)
INTERNAL LATCH ADDRESS COUNTER
N D (N )
D (N ) D (N +1)
D (N +1) D (N +2)
D (N +2) D (N +3)
Figure 7.2
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7.3 DISPLAY DATA RAM (DDRAM)
7.3.1 DDRAM
It is 98 X 70 X 16 bits capacity RAM prepared for storing dot data. Refer to the following memory map for the RAM configuration.
Memory Map
RGB alignment Data control command
(MADCTR) MX=0 (MADCTR) MX=1 Color Data Page (MADCTR)
MY=0
Column 0 97 R G B R 1 96 G B R 97 0 G B
(MADCTR)
MY=1
0 1 2 3 4 5 6 7 : 62 63 64 65 66 67 68 69 SEGout
69 68 67 66 65 64 63 62 : 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
You can change position of R and B with MADCTR command.
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Address Counter
The address counter sets the addresses of the display data RAM for writing. Data is written pixel into the RAM matrix of ST7628. The data for one pixel or two pixels is collected (RGB 5-6-5-bit), according to the data formats. As soon as this pixel-data information is complete, the "Write access" is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=97 (61hex) and Y=0 to Y=69 (45h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined into which will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=97 (61h), YE=69 (45h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (MV=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands "CASET, RASET" and "MADCTR" (see section "9.1.31"), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Figure 7.3 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the databus be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as below:
Condition When RAMWR command is accepted
Column Counter Return to "Start Column (XS)"
Row Counter Return to "Start Row (YS)" No change
Complete Pixel Read / Write action
Increment by 1
The Column counter value is larger than "End Column (XE)"
Return to "Start Column (XS)"
Increment by 1
The Column counter value is larger than "End Column (XE)" and the Row counter value is larger than "End Row (YE)"
Return to "Start Column (XS)"
Return to "Start Row (YS)"
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Display Data Direction Normal MADCTR Parameter MV 0 MX 0 MY 0 Image in the Host (MPU) Image in the Driver (DDRAM)
Y-Mirror
0
0
1
X-Mirror
0
1
0
X-Mirror Y-Mirror
0
1
1
X-Y Exchange
1
0
0
X-Y Exchange Y-Mirror X-Y Exchange X-Mirror X-Y Exchange X-Mirror Y-Mirror
1
0
1
1
1
0
1
1
1
Figure 7.3 Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
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7.3.3 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU's read or write of DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM when the LCD is turned on does not cause troubles such as flicking of the display images.
7.3.4
Scroll Address Circuit
The circuit associates lines on DDRAM with COM output. ST7628 processes signals for the liquid crystal display on 1-line basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in line.
7.3.5
Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM.
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7.3.6 Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, contents of the frame memory within an area where column address is 00h to 61h and row address is 00h to 45h is displayed. To display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0). Example1) Normal Display On
Example2) Partial Display On: PSL[6:0] = 04h, PEL[6:0] = 42h, MADCTR (ML)=0
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7.3.7
Vertical Scroll
Rolling Scroll There is just one types of vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h).
Figure 7.4 Rolling Scroll Definition
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =70. In this case, `rolling' scrolling is applied as shown below. All the memory contents will be used. Example1) Panel size=98(RGB) x 70, TFA =3, VSA=65, BFA=2, SSA=4, MADCTR (ML) =0: Rolling Scroll
SEG94 SEG95 SEG96 SEG96 SEG97 SEG97 SEG0 SEG1 SEG2 SEG3 SEG4 : : :
Example2) Panel size=98(RGB) x 70, TFA =3, VSA=65, BFA=2, SSA=4, MADCTR (ML) =1: Rolling Scroll
SEG94 SEG95 SEG0 SEG1 SEG2 SEG3 SEG4 : : :
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Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands " Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h). Case 1: TFA + VSA + BFA<70 N/A. Do not set TFA + VSA + BFA<70. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=70 (Rolling Scrolling) Example1) When MADCTR parameter ML="0", TFA=0, VSA=70, BFA=0 and VSCSAD=40.
2 1 1 2 2 1 1 2
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Example2) When MADCTR parameter ML="1", TFA=10, VSA=60, BFA=0 and VSCSAD=30.
2
3
2
1
3
1
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1
2
3
1
2
3
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7.3.8 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
Tearing Effect Line Modes(Frame rate=77Hz)
FRAME COM scan internal signal
1st line 2nd line 3rd line
Frame1
Frame2
61th line
70th line
TE (mode 1)
tHDH tHDH
tVDH tCYCLE
TE (mode 2)
tHCYC 61 line 70 line
tVDH
9 line
61 line 70 line
9 line
Mode 1, the Tearing Effect Output signal consists of V-Sync(tVDH) information. It starts at 61th line signal and ends at the 70th line signal. There is one high pulse during each frame. Mode 2, the Tearing Effect Output signal consists of both H-Sync(tHDH) and V-Sync(tVDH) information. TE pin output tHDH pulse on each COM scan signal. During 61th ~ 70th line signal, it output a high pulse which equals 1 tHDH + 1 tVDH.
Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low.
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Tearing Effect Line Timing
The Tearing Effect signal is described below:
Table 7.3.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 77Hz, N-line = 0x01, Vop=12V, VDDI/VDDA=1.8V/2.8V)
Symbol tVDL tVDH tHDL tHDH Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing High Duration Min -1 -11 Typ 13 1.6 185 12 Max ----Unit ms ms us us Mode2 description Mode1
Note: The signal's rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
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Example 1: MPU Write is Faster than Panel Read.
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
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Example 2: MPU Write is Slower than Panel Read
MCU to Memory
1
TE Output Signal
st
70
th
time
Memory to LCD
1
Image on LCD
st
70
b c
th
time d e f
a
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer "catches" the MPU to Frame memory write position.
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7.4 Gary-Scale Display
ST7628 incorporates a 4FRC & 31 PWM function circuit to display a 64 gray-scale display.
7.5 Oscillation circuit
ST7628 is built-in an oscillator circuit. It provides internal clock without external resistor. This oscillator signal is used in the voltage converter and display timing generation circuit.
7.6 Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, which is generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 96-bits display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 7.5.
Figure 7.5 2-frame AC Driving Waveform (Duty Ratio: 1/70)
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Figure 7.6 N-Line Inversion Driving Waveform (N=5, Duty Ratio=1/70)
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7.7 POWER LEVEL DEFINITION
7.7.1 Power ON/OFF SEQUENCE
VDDI and VDDA can be applied in any order. (VDDI=VDD, VDDA=VDD2, VDD3, VDD4, VDD5) VDDI and VDDA can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDDA and VDDI must be powered down minimum 120msec after /RST has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDDA can be powered down minimum 0msec after /RST has been released. /CS can be applied at any timing or can be permanently grounded. /RST has priority over /CS. There will be no damage to the display module if the power sequences are not met. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. If /RST line is not held stable by host during Power On Sequence as defined in Sections case1 and case2, then it will be necessary to apply a Hardware Reset (/RST) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below:
Case 1 - /RST line is held High or Unstable by Host at Power On
If /RST line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDDA and VDDI have been applied - otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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Case 2 - /RST line is held Low by host at Power On
If /RST line is held Low (and stable) by the host during Power On, then the /RST must be held low for minimum 10sec after both VDDA and VDDI have been applied.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
UNCONTROLLED POWER OFF
The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects within 1 second on the display (blank display) and remains blank until "Power On Sequence" powers it up.
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7.7.2 Power Levels
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption:
1. Normal Mode On (full display), Idle Mode Off, Sleep Out:
In this mode, the display is able to show maximum 65K colors.
2. Partial Mode On, Idle Mode Off, Sleep Out:
In this mode part of the display is used with maximum 65K colors.
3. Normal Mode On (full display), Idle Mode On, Sleep Out:
In this mode, the full display area is used but with 8 colors.
4. Partial Mode On, Idle Mode On, Sleep Out:
In this mode, part of the display is used but with 8 colors.
5. Sleep In Mode:
In this mode, the DC:DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with Digital VDD power supply. Contents of the memory are safe.
6. Power Off Mode:
In this mode, both Analog VDD and Digital VDD are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
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7.7.3 POWER FLOW CHART FOR DIFFERENT POWER MODES
Normal display mode on = NORON Partial mode on = PTLON Idle mode off = IDMOFF
Idle mode on = IDMON Sleep out = SLPOUT Sleep in = SLPIN
Power on sequence
HW reset SW reset
NORON PTLON Sleep out Normal display mode on Idle mode off
SLPIN Sleep in Normal display mode on Idle mode off
NORON
SLPOUT
PTLON
IDMON
IDMOFF
IDMON
IDMOFF
SLPIN Sleep out Normal display mode on Idle mode on Sleep in Normal display mode on Idle mode on
SLPOUT
SLPIN Sleep out Partial mode on Idle mode off Sleep in Partial mode on Idle mode off
SLPOUT
IDMON
IDMOFF SLPIN Sleep out Partial mode on Idle mode on
IDMON
IDMOFF PTLON Sleep in Partial mode on Idle mode on
PTLON
SLPOUT
NORON
NORON
Sleep out
Sleep in
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode.
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7.8 Color Depth Conversion Look Up Tables
Color Look Up Table Inputs 256 Color Data 4096 Color Data Look Up Table Outputs Frame Memory Data (5 or 6-bit) Default Value RGBSET parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
RED
000 001 010 011 100 101 110 111 Dummy input
GREEN
000 001 010 011 100 101 110 111 Dummy input
BLUE
00 01 10 11 Dummy input
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
R004 R003 R002 R001 R000 R014 R013 R012 R011 R010 R024 R023 R022 R021 R020 R034 R033 R032 R031 R030 R044 R043 R042 R041 R040 R054 R053 R052 R051 R050 R064 R063 R062 R061 R060 R074 R073 R072 R071 R070 R084 R083 R082 R081 R080 R094 R093 R092 R091 R090 R104 R103 R102 R101 R100 R114 R113 R112 R111 R110 R124 R123 R122 R121 R120 R134 R133 R132 R131 R130 R144 R143 R142 R141 R140 R154 R153 R152 R151 R150 G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 B004 B003 B002 B001 B000 B014 B013 B012 B011 B010 B024 B023 B022 B021 B020 B034 B033 B032 B031 B030 B044 B043 B042 B041 B040 B054 B053 B052 B051 B050 B064 B063 B062 B061 B060 B074 B073 B072 B071 B070 B084 B083 B082 B081 B080 B094 B093 B092 B091 B090 B104 B103 B102 B101 B100 B114 B113 B112 B111 B110 B124 B123 B122 B121 B120 B134 B133 B132 B131 B130 B144 B143 B142 B141 B140 B154 B153 B152 B151 B150
00000 00010 00100 00110 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11100 11111 000000 000100 001000 001100 010000 010100 011000 011100 100000 100100 101000 101100 110000 110100 111000 111111 00000 00010 00100 00110 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11100 11111
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7.9 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction.
DC/DC Booster Block Diagram
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7.9.1 Voltage Regulator Circuits
SET V0 (Temperature = 24)
V0=a+{Vop[8:0] + VopOffset[8:0]+ (EV[6:0]-3Fh)}xb
Example: Vop[8:0]=011010010 VopOffset[8:0]=000000011 EV[6:0]=0111111 V0=3.6 + ( 210 + 3 + (63-63) ) x 0.04 =12.12 (V)
(V)
a is a fixed constant value (seeTable 7.9.1). b is a fixed constant value (seeTable 7.9.1). Vop [8:0] is the programmed VOP value. The programming range for Vop[8:0] is 5 to 410 (19Ahex). The range of contrast is 128 steps for fine tuning VOP.
Table 7.9.1
SYMBOL a b VALUE 3.6 0.04 UNIT V V
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The Vop [8:0] value must be in the V0 programming range as given in Figure 7.7. Evaluating V0 equation, values outside the programming range indicated in many result.
As the programming range for the internally generated V0 voltage is above the limited V0 (18V), users has to ensure while setting the VOP register and selecting the temperature compensation that under all conditions and including all tolerances that the V0 voltage remains below 18V. SET V0 with temperature compensation (Temperatue 24)
compensation coefficiency for each temperature step. Each temperature step is 8oC. Please see Figure 7.8 as below.
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a = 3.6V
Figure 7.7 V0 programming range
There are 16-line slope in each temperature steps and customer can select one line slope of temperature
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V0(V)
16-line slope
-40
-32
~
-8
16
24
32
40
~
80
88
Temperature (o C)
Figure 7.8
In command TEMPSEL (see section 9.1.72) each MTx, where x=0, 1, 2,..., E, F, has a value between 0 and 15. MTx = 0 results in 0V increment on V0, MTx = 1 results in Mx=5mV increment, ..., MTx = 15 results in Mx=15x5mV=75mV increment. Note that each MTx individually corresponds to a temperature interval; The relations between Mx and V0 quantity due to temperature V0(T) are described in the equations shown as follows: Temperature range -40 T -32 -32 T -24 -24 T -16 -16 T -8 -8 T 0 0 T 8 8 T 16 16 T 24 24 T 32 32 T 40 40 T 48 48 T 56 56 T 64 64 T 72 72 T 80 80 T 88 Equation V0(V) at temperature=T V0(T) = V0(T24)+ (-32-T)M0 +( M1 + M2 + M3 + M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (-24-T)M1 +( M2 + M3 + M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (-16-T)M2 +( M3 + M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (-8-T)M3 +( M4 + M5 + M6 + M7)8 V0(T) = V0(T24)+ (0-T)M4 +( M5 + M6 + M7)8 V0(T) = V0(T24)+ (8-T)M5 +( M6 + M7)8 V0(T) = V0(T24)+ (16-T)M6 + M78 V0(T) = V0(T24)+ (24-T)M7 V0(T) = V0(T24)(T-24)M8 V0(T) = V0(T24)(T-32)M9M88 V0(T) = V0(T24)(T-40)M10(M9 + M8 )8 V0(T) = V0(T24)(T-48)M11(M10 + M9 + M8 )8 V0(T) = V0(T24)(T-56)M12(M11 + M10 + M9 + M8 )8 V0(T) = V0(T24)(T-64)M13(M12 + M11 + M10 + M9 + M8 )8 V0(T) = V0(T24)(T-72)M14(M13 + M12 + M11 + M10 + M9 + M8 )8 V0(T) = V0(T24)(T-80)M15( M14 + M13 + M12 + M11 + M10 + M9 + M8 )8
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Setting example for default TC curve COMMAND 0xF4 DATA 1 : 0x50 3 : 0x25 5 : 0x35 7 : 0xAA
th th rd st
2 : 0x00 4 : 0x61 6 : 0x64 8 : 0xFF
th th th
nd
Vop=11.72, BIAS=1/8, Default TC
14.00 Default TC 12.00
10.00
8.00 VOP 6.00 4.00 2.00 0.00 -30 -20 -10 0 10 20 Temp. 30 40 50 60 70 80
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Setting example for -0.04%/ TC curve COMMAND 0xF4 DATA 1 : 0x01 3 : 0x01 5 : 0x01 7 : 0x01
th th rd st
1 : 0x01 3 : 0x01 5 : 0x01 7 : 0x01
th th rd
st
Vop=11.72, BIAS=1/8, -0.04%/ 14.00 TC (-0.04%/) 12.00
10.00
8.00 VOP 6.00 4.00 2.00 0.00 -30 -20 -10 0 10 20 Temp. 30 40 50 60 70 80
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Setting example for -0.07%/ TC curve COMMAND 0xF4 DATA 1 : 0x02 3 : 0x02 5 : 0x02 7 : 0x02
th th rd st
1 : 0x02 3 : 0x02 5 : 0x02 7 : 0x02
th th rd
st
Vop=11.72, BIAS=1/8, -0.07%/ 14.00 TC (-0.07%/) 12.00
10.00
8.00 VOP 6.00 4.00 2.00 0.00 -30 -20 -10 0 10 20 Temp. 30 40 50 60 70 80
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-0.11%/ TC Curve example COMMAND 0xF4 DATA 1 : 0x03 3 : 0x03 5 : 0x03 7 : 0x03
th th rd st
1 : 0x03 3 : 0x03 5 : 0x03 7 : 0x03
th th rd
st
Vop=11.72, BIAS=1/8, -0.11%/ 14.00 TC (-0.11%/) 12.00
10.00
8.00 VOP 6.00 4.00 2.00 0.00 -30 -20 -10 0 10 20 Temp. 30 40 50 60 70 80
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V0 fine tuning ST7628 has 2 commands for fine tuning V0. These commands are VopOfsetInc (see section 9.1.48) and VopOfsetDec (see section 9.1.49). When writing VopOfsetInc into IC for each time, V0 would increase 40mV; when writing VopOfsetDec into IC for each time, V0 would decrease 40mV. Example: Vop[8:0]=011010010 Vopoffset[8:0]=000000011 EV[6:0]=0111111 VopOfsetInc x2 V0=3.6 +( 210 +3+ (63-63) +2 } x 0.04 =12.2 (V)
7.9.2
Voltage Follower Circuits
There is a built-in voltage follower circuits in ST7628 for generating Vg and Vm. These voltages are decided by bias ratio selection circuitry which is set by users with software to control 1/5 to 1/12 bias ratios to match the optimum display performance of LCD panel. Bias driving rule is listed below: LCD bias 1/N bias Vg (2/N) x V0 Vm (1/N) x V0
N=5 to 12 7.9.3 OTP Setting Flow
OTP Setting Flow ST7628 provide the Write and Read function to write the Electronic Control value and Built-in resistance ratio into and read them from the built-in OTP. Using the Write and Read functions, you can store these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel's voltage. But using this function must attention the setting procedure. Please see the following diagram.
Figure 7.9 V0 value control for different modules by loading OTP offset
Note1: This setting flow is used for LCM assembler. Note2: OTP shouldn't be written without preceding loading correctly from OTP to avoid some errors during IC operation. Note3: When writing value to OTP, the voltage of VPP must be more than 7.5V(7.5V~7.75V); the current of Ivpp must be more than 4 mA. Note4: If the OTP is exposed to a high temperature for hours, data in the memory cell may probably be lost before the data retention guarantee period. To retain data in the memory cell, keep the memory cell below 90. The data retention guarantee period is specified including the retention period.
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7.9.4 Frquency Temperature Gradient Compensation Coefficient
ST7628 will auto-switch frame rate on different temperature such as Figure 11.1. TA, TB and TC are frame rate switching temperatures which can be defined by customer with command TMPRNG(see section 9.1.70). FA, FB, FC and FD are switched frame rate which also can be defined by customer with command FRMSEL (see section 9.1.68). The frame rate range is from 37.5Hz to 170Hz. When the temperature is in increasing state, frame rate changes to the higher step at TA/TB/TC+TH(). When the temperature is in decreasing state, frame rate changes to the lower step at TA/TB/TC. For example: TC=10 and TH=5, FC switches to FD at 15 but FD switches to FC at 10. Please take Figure 11.1for reference.
Figure 7.10
Note: Please make sure to avoid any kind of heating source closing to ST7628 such as back light, to prevent Vop is not anticipatve because of temperature compensate circuit worked.
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7.10 Sleep Out -Command and Self-Diagnostic Functions of the Display Module
7.10.1 Register loading Detection Sleep Out-command is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from OTP ROM (or similar device) to registers of the display controller is working properly.
There are compared factory values of the OTP ROM and register values of the display controller by the display controller (1st step: compares register and OTP ROM values, 2nd step: loads OTP ROM values to registers). If those both values (OTP ROM and register values) are same, there is inverted (= increased by 1) a bit, which is defined in command RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= not increased by 1). The flow chart for this internal function is following:
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7.10.2 Functionality Detection Sleep Out-command is a trigger for an internal function of the display module. The internal function (= the display controller) is comparing if the display module is still meeting functionality requirements (e.g. booster voltage levels, timings, etc.). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command Read Display Self-Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= not increased by 1). The flow chart for this internal function is following:
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In -mode to Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR's D6 is valid. Otherwise, there is 5msec delay for D6's value, when Sleep Out -command is sent in Sleep Out -mode.
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8. RESET value
Item
Frame memory (RAM data) RDDID RDDPM RDDMADCTR RDDCOLMOD RDDIM RDDSM RDDSDR Sleep In/Out Display mode (normal/partial) Display Inversion On/Off All Pixel Off mode All Pixel On mode Contrast (EV) Display On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Color set
After Power On
Random 45h,D2h,0Eh 08h 00h 05h (16-Bit/Pixel) 00h 00h 00h In Normal Off Disable Disable 3Fh Display Off 00h 61h 00h 45h Refer to Section 7.8
After Software Reset
No Change 45h,D2h,0Eh 08h No Change No Change 00h 00h 00h In Normal Off Disable Disable 3Fh Display Off 00h 61h (when MV=0) 45h (when MV=1) 00h 45h (when MV=0) 61h (when MV=1) Contents of the look-up table protected
After Hardware Reset
No Change 45h,D2h,0Eh 08h 00h 05h (16-Bit/Pixel) 00h 00h 00h In Normal Off Disable Disable 3Fh Display Off 00h 61h
00h 45h Refer to Section 7.8
Partial: Start Address (PS) Partial: End Address (PE) Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) TE On/Off TE Mode Memory Data Access Control MY/MX/MV/ML/RGB) Scroll Start Address (SSA) Idle Mode On/Off Interface Color Pixel Format (P) ID1[7:0] ID2[6:0] ID3[7:0] Drive Duty First Common FOSC Divider Vop Vop Offset Bias
00h 45h 00h 46h 00h Off 0 (Mode1) 00h 00h Off 05h (16Bit/Pixel) 45h D2h 0Eh 45h 00h No division 0D2h 0000h 1/10 Bias
00h 45h 00h 46h 00h Off 0 (Mode1) No Change 00h Off No change 45h D2h 0Eh 45h 00h No division 0D2h 0000h 1/10 Bias
00h 45h 00h 46h 00h Off 0 (Mode1) 00h 00h Off 05h (16Bit/Pixel) 45h D2h 0Eh 45h 00h No division 0D2h 0000h 1/10 Bias
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Booster setting Booster Efficiency Vg source EPCTIN 8x 01 From VDD2x2 0 8x 01 From VDD2x2 0 8x 01 From VDD2x2 0
OTP selection
Frame Frequency in Normal Color (FA/FB/FC/FD) Frame Frequency in 8-Color (Idle) (F8A/F8B/F8C/F8D) Temperature Range (TA/TB/TC) Temperature Hysteresis (TH) TEMPSEL
Disable
46Hz/61.5Hz/77Hz/82Hz 46Hz/61.5Hz/77Hz/82Hz -16/0/48 5 Refer to 9.1.72
Disable
46Hz/61.5Hz/77Hz/82Hz 46Hz/61.5Hz/77Hz/82Hz -16/0/48 5 Refer to 9.1.72
Disable
46Hz/61.5Hz/77Hz/82Hz 46Hz/61.5Hz/77Hz/82Hz -16/0/48 5 Refer to 9.1.72
Note. Some of above default values can be modified by customer after OTP writing. Please refer to OTPB related register list for the content of OTP.
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9. INSTRUCTIONS
9.1 INSTRUCTION table
Command Table-1 , /EXT= H , L, or floating
Hex Command
(00h) NOP (01h) SWRESET (04h) RDDID (09h) RDDST (0Ah) RDDPM (0Bh) RDDMADCTR (0Ch) RDDCOLMOD (0Dh) RDDIM (0Eh) RDDSM -
A0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
/RD /WR 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
D7 0 0 0 -
D6 0 0 0 -
D5 0 0 0 -
D4 0 0 0 -
D3 0 0 0 -
D2 0 0 1 -
D1 0 0 0 -
D0 0 1 0 -
Function
No Operation Software reset Read Display ID Dummy read
Ref 9.1.1 9.1.2 9.1.3
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read (D23-D16) 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read (D15-D8)
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ID3 read (D7-D0) 0 0 0 0 1 0 0 1 Read Display Status Dummy read
9.1.4
ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 (D31-D24) ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 (D23-D16) ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST8 (D15-D8) ST0 (D7-D0)
0 D7 0 D7 0 0 0 D7 0 D7 0 D7
0 D6 0 D6 0 0 0 0 0 D6 0 D6
0 D5 0 D5 0 0 0 D5 0 0 0 D5
0 D4 0 D4 0 0 0 D4 0 0 0 D4
1 D3 1 D3 1 0 1 D3 1 0 1 0
0 D2 0 0 1 D2 1 0 1 0 1 0
1 0 1 0 0 D1 0 0 1 0 1 0
0 0 1 0 0 D0 1 0 0 0 1
Read Display Power Mode Dummy read Read Display MADCTR Dummy read Read Display Pixel Format Dummy read Read Display Image Mode Dummy read Read Display Signal Mode Dummy read Read Display Self-diagnostic
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
(0Fh) RDDSDR -
9.1.10
result
0
Dummy read -
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(10h) SLPIN (11h) SLPOUT (12h) PTLON (13h) NORON (20h) INVOFF (21h) INVON APOFF (22h)
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 1 1 1
1 1 1 1 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 1 1 0 0 1
0 1 0 1 0 1 0
Sleep in & booster off Sleep out & booster on Partial mode on Partial off (Normal)
9.1.11 9.1.12 9.1.13 9.1.14
Display inversion off (normal) 9.1.15 Display inversion on All pixel off (Only for test purpose)
9.1.16 9.1.17
APON (23h)
All pixel on (Only for test
9.1.18
0 0 1 0 0 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
D7
0 0
EV6
1 1
EV5
0 0
EV4
0 0
EV3
0 1
EV2
1 0
EV1
1
purpose)
(25h) WRCNTR (28h) DISPOFF (29h) DISPON (2Ah) CASET
1
Write contrast
9.1.19
EV0 EV = 0 to 127
0 0 0
XS6 XE6
1 1 1
XS5 XE5
0 0 0
XS4 XE4
1 1 1
XS3 XE3
0 0 0
XS2 XE2
0 0 1
XS1 XE1
0 1 0
Display off Display on Column address set
9.1.20 9.1.21 9.1.22
XS0 X_ADR start: 0XS61h XE0 X_ADR end: XSXE 61h
(2Bh) RASET
0 1 1
0
YS6 YE6
1
YS5 YE5
0
YS4 YE4
1
YS3 YE3
0
YS2 YE2
1
YS1 YE1
1
Row address set
9.1.23
YS0 Y_ADR start: 0YS45h YE0 Y_ADR end: YSYE45h
(2Ch) RAMWR
0 1
0
D6
1
D5
0
D4
1
D3
1
D2
0
D1
0
D0
Memory write Write data Color set for 256 or 4k color
9.1.24
(2Dh) RGBSET -
0 1 1 1 1 1 1 1 1 1
0
: : : -
0
: : : -
1
R5 : R5 G5 : G5 B5 : B5
0
R4 : R4 G4 : G4 B4 : B4
1
R3 : R3 G3 : G3 B3 : B3
1
R2 : R2 G2 : G2 B2 : B2
0
R1 : R1 G1 : G1 B1 : B1
1
display R0 : R0 G0 : G0 B0 : B0 Red tone (00000) :Red tone (11111) Green tone (000000) :Green tone (111111) Blue tone (00000) :Blue tone (11111) Memory Read Dummy read
9.1.25
(2Eh) RAMRD
0 1 1
0 D7
0 D6
1 D5
0 D4
1 D3
1 D2
1 D1
0 D0
9.1.26
(30h) PTLAR
0
0
0
1
1
0
0
0
0
Partial start/end address set
9.1.27
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(33h) SCRLAR (34h) TEOFF (35h) TEON (36h) MADCTR (37h) VSCSAD
1 1 0 1 1 1 0 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1
0 0 0 0 0 0 0 0 0 MY 0 0 0 0 0 1 -
PS6 PE6
PS5 PE5
PS4 PE4
PS3 PE3
PS2 PE2
PS1 PE1
PS0 Start address (0~69) PE0 End address (0~69)
0
1
1
0
0
1
1
Scroll Area
9.1.28
TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 TFA= 0~70 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 VSA= 0~70 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 BFA= 0~70
0 0 0 MX 0
1 1 1 MV 1
1 1 1
0 0 0
1 1 1 1
0 0 1 1
0 1 M 0 1
Tearing effect line off Tearing effect mode set & on "0": mode1, "1": mode2 Memory data access control Scroll start address of RAM
9.1.29 9.1.30
9.1.31
ML RGB 1 0
9.1.32
SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 SSA = 0~69
(38h) IDMOFF (39h) IDMON (3Ah) COLMOD (DAh) RDID1 (DBh) RDID2 (DCh) RDID3 -
0 0 0 1 0 1 1 0 1 1 0 1 1
0 0 0 1 -
1 1 1 0 -
1 1 1 1 -
1 1 1 1 -
0 0 0 P2 0 -
0 0 1 P1 1 -
0 1 0 P0 0 -
Idle mode off Idle mode on Interface pixel format Interface format Read ID1 Dummy read
9.1.33 9.1.34 9.1.35
9.1.36
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 (D7-D0) 1 1 0 1 1 0 1 1 Read ID2 Dummy read
9.1.37
ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 (D7-D0) 1 1 0 1 1 1 0 0 Read ID3 Dummy read
9.1.38
ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 (D7-D0)
Note 1: When /EXT connects to H or floating, commands which are not defined in "Command Table-1" are treated as NOP (00H) command. Note 2: Commands 10H, 12H, 13H, 20H, 21H, 25H, 28H, 29H, 30H, 36H (Bit ML only), 38H and 39H are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09H), Read Display Power Mode (0AH), Read Display MADCTR (0BH), Read Display Pixel Format (0CH), Read Display Image Mode (0DH), Read Display Signal Mode (0EH) and Read Display Self Diagnostic Result (0FH) of these commands is updated immediately both in Sleep In mode and Sleep Out mode.
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Command Table-2 , /EXT= L
Hex Command
(B0h) DutySet
A0 0 1
/RD /WR 1 1 1 1 1 1 1
1
D7 1 0 1 1 1
PTLM
D6 0
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
Function Display Duty setting
Ref 9.1.39
0 0 0 0 0 0 0
0
Du6 Du5 Du4 Du3 Du2 Du1 Du0 0 F6 0 0
0
(B1h) FirstCom
0 1
1 F5 1 1
0
1 F4 1 1
1
0 F3 0
-
0 F2 0 1
0
0 F1 1
1 F0 1
First Com. Page address
9.1.40
(B3h) OscDiv
0 1
FOSC divider
9.1.41
CLD1 CLD0
Partial Saving Power
(B4h) PTLMOD
9.1.42
0
1
0
1
0
0
0 Mode Selection
0
(B5h) NLInvSet
0 1
1 1 1 1 1
0 0 0 0 0
1 M 1
0 N6 0
1 N5 1
1 N4 1
0 N3 0
SBGR
1 N2 1
-
0 N1 1
-
1 N0
N-line control
9.1.43
Com/Seg Scan Direction
(B7h) ComScanDir
9.1.44
0 1
1 for Glass layout
-
SMY SMX SINV SML 1 0 1 1
read modify write control
(B8h) RmwIn
9.1.45
0
1
0
0
0 IN read modify write control
9.1.46
(B9h) RmwOut (C0h) VopSet
0 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1
0 1
1 0
1 0
1 0
0 0
0 0
1 Out 0 Vop setting
9.1.47
Vop7 Vop6 Vop5 Vop4 Vop3 Vop2 Vop1 Vop0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Vop8 1 0 1 +40mv/setp -40mv/setp Bias selection
9.1.48 9.1.49 9.1.50
(C1h) VopOfsetInc (C2h) VopOfsetDec (C3h) BiasSel
0 0 0 1
Bias2 Bias1 Bias0
(C4h) BstBmpXSel
0 1
1
0
0
Booster setting
9.1.51
BST2 BST 1 BST0
Booster efficiency
(C5h) BstEffSel
9.1.52
0 1
1 1
0
1 selection
BTF1 BTF0 1 1 Vop offset fuse bit adjust
9.1.53
(C7h) VopOffset
0 1 1
VOS7 VOS6 VOS5 VOS4 VOS3 VOS2 VOS1 VOS0
1
1
0
0
1
0
1
VOS8
FV3 with Booster x2
(CBh) VgSorcSel
9.1.54
0
1 control
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1
(CCh) ID1Set
1 1 1 1 1 1 1 1 1 1
1
0 0 0 0 0 0 0 0 0 0
0
1
1
0
0
1
1
0
2BT0 0 ID1 setting
9.1.55
0 1
ID1_7 ID1_6 ID1_5 ID1_4 ID1_3 ID1_2 ID1_1 ID1_0
(CDh) ID2Set
0 1
1
1
1
0
0
1
1
0
1
ID2 setting
9.1.56
ID2_6 ID2_5 ID2_4 ID2_3 ID2_2 ID2_1 ID2_0
(CEh) ID3Set
0 1
1
1
0
0
1
1
1
0
ID3 setting
9.1.57
ID3_7 ID3_6 ID3_5 ID3_4 ID3_3 ID3_2 ID3_1 ID3_0
(D0h) ANASET
0 1
1 0 1
EXTE
1 0 1
OTPBE
0 0 0
0
0 1 1
ARD
0 1 0
1
0 1 1
1
0 0 1
1
0 1
Analog circuit setting
9.1.58
mask rom data auto
(D7h) AutoLoadSet
9.1.59
0
1
1 re-load control
1
(DEh) RDTstStatus
0 1 1
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 -
1 -
0 -
1 -
1 -
1 -
1 -
0 -
read IC status Dummy Read OTP / RDA / PWR_VOP
9.1.60
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 read control 1 0 1 1 1 1 1 0
/XRD
(E0h) EPCTIN
0 1
1
WR
0 0
0 0
0 0
0 0
0 0
Control OTP WR/RD
9.1.61
(E1h) EPCTOUT (E2h) EPMWR (E3h) EPMRD (E4h) OTPSEL
0 0 0 0 1
1 1 1 1
1 1 1 1 0 1 0 1 1 1
0 0 0 0 1 1 0 0 1
0 0 0 0 1 0 1 0
0 0 0 1 0 1 0 1
0 1 1 0 0 0 0 1
1 0 1 0 0
OTP control cancel Write to OTP Read from OTP Select OTP
9.1.62 9.1.63 9.1.64 9.1.65
MS1 MS0 0 0 1 1 1 1 0 1 1 1
Programmable rom
(E5h) ROMSET
9.1.66
0 1
1
setting
1 0 Fuse data readout control
9.1.66
(E6h) StusRDSEL
0 1
STU3 STU2 STU1 STU0
Frame Freq. in Temp
(F0h) FRMSEL
9.1.68
0 1 1 1 1
0
0
0
0 range A,B,C and D
FA4 FA3
FA2 FA1 FA0
FB4 FB3 FB2 FB1 FB0 FC4 FC3 FC2 FC1 FC0 FD4 FD3 FD2 FD1 FD0 Frame Freq. in Temp
9.1.69
(F1h) FRM8SEL
0
1
0
0
0
1 range A,B,C and D (idle)
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1 1 1 1
(F2h) TMPRNG
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1
1 TA6
1 TA5
F8A4 F8A3 F8A2 F8A1 F8A0 F8B4 F8B3 F8B2 F8B1 F8B0 F8C4 F8C3 F8C2 F8C1 F8C0 F8D4 F8D3 F8D2 F8D1 F8D0 1 TA4 0 TA3 0 TA2 1 TA1 0 TA0 Temp range A,B and C
9.1.70
0 1 1 1
TB6 TB5 TB4 TB3 TB2 TB1 TB0 TC6 TC5 TC4 TC3 TC2 TC1 TC0 1 1 1 1 1 1 0 0 1 1 Hysteresis value set
9.1.71
(F3h) TMPHYS
0 1
TH3 TH2 TH1 TH0 0 1 0 0 TEMPSEL
9.1.72
(F4h) TEMPSEL
0 1 1 1 1 1 1 1 1
MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00 MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20 MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40 MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60 MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80 MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0 MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0 MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0
Temperature detection
(F7h) THYS
9.1.73
0 1
1
1
1
1
0
1
1
1 threshold
THYS7 THYS6 THYS5 THYS4 THYS3 THYS2 THYS1 THYS0
Set Frame RGB PWM
(F9h) Frame Set
9.1.74
0 1 1
1 -
1
1 -
1
1
0
0
1 value
:
P14 P13 P24 P23
P12 P11 P10 P22 P21 P20
:
1 1
:
1 1
:
0 0
:
-
:
-
:
:
:
:
:
-
P154 P153 P152 P151 P150 P164 P163 P162 P161 P160
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OTPB related register list function Bias[2:0] Bst2_XEVD SMY Register 0xC3[2:0] 0xCB[0] 0xB7[7] function BstPumpX[2:0] ID1[7:0] SMX Register 0xC4[2:0] 0xCC[7:0] 0xB7[6] function BstFreq[1:0] ID3[7:0] SBGR Register 0xC5[1:0] 0xCE[7:0] 0xB7[3]
OTP related register list function PTLMOD ID2[6:0] Register 0xB4[7] 0xCD[6:0] function NLMod[7], N_line[6:0] ExtCmdEn Register 0xB5[7:0] 0xD7[7] function VopOfst1[8:0] OTPBEn Register 0xC7[8:0] 0xD7[6]
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9.1.1 NOP(00h)
A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Hex
(00h)
Command
NOP Parameter
No Parameter
Description
This command is empty command. It does not have effect on the display module. However it can be used to terminate RAM data write as described in RAMWR (Memory Write) and parameter write commands.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
-
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9.1.2 SWRESET: Software Reset(01h)
A0 0 /RD 1 /WR 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 Hex
(01h)
Command
SWRESET Parameter
No Parameter
Description
When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all segment & common outputs are set to Vm (display off: blank display). (See default tables in each command description) Note: The Frame Memory contents are not affected by this command.
Restriction
It will be necessary to wait 5msec before sending new command following software reset. The display module loads all display supplier's factory default values to the registers during 5msec. If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. Software Reset command cannot be sent during Sleep Out sequence.
Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
SWRESET Command
Display whole blank screen
Parameter
Display
Set Command s to S/W Default Value
Action
Sleep In Mode Mode
Sequential transter
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9.1.3 RDDID: Read Display ID (04h)
A0 0 1 1 1 1 /RD 1 0 0 0 0 /WR 0 1 1 1 1 D7 0 ID17 1 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 Hex
(04h) -
Command
RDDID
Dummy Read 2nd parameter 3rd parameter 4th parameter NOTE: "-" Don't care Description
ID10 ID20 ID30 -
This read byte returns 24-bit display identification information. The 1st parameter is dummy data The 2nd parameter (ID17 to ID10): LCD module's manufacturer ID. The 3rd parameter (ID26 to ID20): LCD module/driver version ID The 4th parameter (ID37 to ID30): LCD module/driver ID. NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value ID1 Power On Sequence S/W Reset H/W Reset 45h 45h 45h ID2 D2h D2h D2h ID3 0Eh 0Eh 0Eh
Default
Status
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Flow Chart
Serial I/F Mode
Read 04h
Parallel I/F Mode Legend
Read 04h
Host Display
Dummy Clock Dummy Read
Command
Parameter
Display Send 2nd parameter Send 2nd parameter Action
Send 3rd parameter
Send 3rd parameter
Mode
Sequential transter Send 4th parameter Send 4th parameter
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9.1.4 RDDST: Read Display Status (09h)
A0 0 1 1 1 1 1 /RD 1 0 0 0 0 0 /WR 0 1 1 1 1 1 D7 0 ST31 ST23 ST15 ST7
Command
RDDST
D6 0 ST30 ST22 ST14 ST6
D5 0 ST29 ST21 ST13 ST5
D4 0 ST28 ST20 ST12 ST4
D3 1 ST27 ST19 ST11 ST3
D2 0 ST26 ST18 ST10 ST2
D1 0 ST25 ST17 ST9 ST1
D0 1 ST24 ST16 ST8 ST0
Hex
(09h) -
Dummy Read 2nd parameter 3rd parameter 4th parameter 5th parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit ST31 ST30 ST29 ST28
Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Order (MV)
Value "1"=Booster on, "0"=off "1"=Decrement, "0"=Increment "1"=Decrement, "0"=Increment "1"= Row/column exchange (MV=1) "0"= Normal (MV=0)
ST27 ST26 ST25 ST24 ST23
Scan Address Order (ML) RGB/BGR Order (RGB) Not Used Not Used Not Used Interface Color Pixel Format Definition
"1"=Decrement, "0"=Increment "1"=BGR, "0"=RGB "0" "0" "0" "010" = 8-bit / pixel, "011" = 12-bit / pixel type A "100" = 12-bit / pixel type B "101" = 16-bit / pixel, "110" = 18-bit / pixel, "111" = 24-bit / pixel, "1" = On, "0" = Off "1" = On, "0" = Off "1" = Out, "0" = In "1" = Normal Display, "0" = Partial Display "1" = Scroll on, "0" = Scroll off "0" "1" = On, "0" = Off "1" = mode On, "0" = mode Off "1" = mode On, "0" = mode Off "1" = On, "0" = Off "1" = On, "0" = Off "0" "0" "0" "0" = mode1, "1" = mode2 "0" "0" "0"
ST22 ST21 ST20
ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2
Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status Not Used Inversion Status All Pixels On All Pixels Off Display On/Off Tearing effect line on/off Not Used Not Used Not Used Tearing effect line mode Not Used Not Used Not Used
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ST0 Not Used "0"
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (ST31 to ST0) 0000 0000_0101 0001_0000 0000_0000 0000 0xxx xx00_0xxx 0001_0000 0000_0000 0000 0000 0000_0101 0001_0000 0000_0000 0000
Flow Chart
Serial I/F Mode
Read 09h
Parallel I/F Mode
Read 09h
Legend
Command
Dummy Clock
Dummy Read
Parameter
Display Send 2nd parameter Send 2nd parameter
Action Send 3rd parameter Send 3rd parameter Mode
Send 4th parameter
Send 4th parameter
Sequential transter
Send 5th parameter
Sendth parameter
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9.1.5 RDDPM: Read Display Power Mode (0Ah)
A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 0 D2 D1 1 0 D0 0 0 Hex
(0Ah) -
Command
RDDPM Dummy Read 2nd parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Booster Voltage Status Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Display On/Off Not Used Not Used Value "1"=Booster on, "0"=Booster off "1" = Idle Mode On, "0" = Idle Mode Off "1" = Partial Mode On, "0" = Partial Mode "1" = Sleep Out, "0" = Sleep In "1" = Normal Display, "0" = Partial Display "1" = Display On, "0" = Display Off "0" "0"
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 0000_1000 (08h) 0000_1000 (08h) 0000_1000 (08h)
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Flow Chart
Legend Serial I/F Mode
RDDPM 0Ah
Parallel I/F Mode
Command RDDPM 0Ah Parameter
Send 2nd parameter
Dummy Read
Display
Action Send 2nd parameter Mode
Sequential transter
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9.1.6 RDDMADCTR: Read Display MADCTR (0Bh)
A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 D3 D2 0 0 D1 1 0 D0 1 0 Hex (0Bh) Command
RDDMADCTR Dummy Read 2nd parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Row Address Order (MY) Column Address Order (MX) Row/Column Order (MV) Scan Address Order (ML) RGB/BGR Order (RGB) Not Used Not Used Not Used Value "1"=Decrement, "0"=Increment "1"=Decrement, "0"=Increment "1"= Row/column exchange (MV=1) "0"= Normal (MV=0) "1"=Decrement, "0"=Increment "1"=BGR, "0"=RGB "0" "0" "0"
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 0000_0000 (00h) No change 0000_0000 (00h)
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Flow Chart
Legend Serial I/F Mode
Read RDDMADCTL
Parallel I/F Mode
Command Read RDDMADCTL Parameter
Send 2nd parameter
Dummy Read
Display
Action Send 2nd parameter
Mode
Sequential transter
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9.1.7 RDDCOLMOD: Read Display Pixel Format (0Ch)
A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 1 0 D2 1 D2 D1 0 D1 D0 0 D0 Hex
(0Ch) -
Command
RDDCOLMOD Dummy Read 2nd parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit D7 D6 D5 D4 D3 D2 D1 D0 Control Interface Color Format Description RGB Interface Color Format Value "0" (Not Used) "0" (Not Used) "0" (Not Used) "0" (Not Used) "0" "010"=8 bit/pixel "011"=12 bit/pixel (type A) "100"=12 bit/pixel (type B) "101"=16 bit/pixel "110"=18 bit/pixel "111"=24 bit/pixel
Restriction
Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 0000_0101 (05h) No change 0000_0101 (05h)
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Flow Chart
Legend Serial I/F Mode
Read RDDCOLMOD
Parallel I/F Mode
Command Read RDDCOLMOD
Host Display
Send 2nd parameter Dummy Read
Parameter
Display
Action Send 2nd parameter Mode
Sequential transter
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9.1.8 RDDIM: Read Display Image Mode (0Dh)
A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 D7 D6 0 0 D5 0 D5 D4 0 D4 D3 1 D3 D2 1 0 D1 0 0 D0 1 0 Hex
(0Dh) -
Command
RDDIM Dummy Read 2nd parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Vertical Scrolling On/Off Horizontal Scrolling On/Off Inversion On/Off All Pixels On All Pixels Off Undefine Value "1" = Vertical scrolling is On, "0" = Vertical scrolling is Off "0" (Not used) "1" = Inversion is On, "0" = Inversion is Off "1" = All Pixels On, "0" = Normal Mode "1" = All Pixels Off, "0" = Normal Mode Undefine
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
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Flow Chart
Legend Serial I/F Mode
Read RDDIM
Parallel I/F Mode
Command Read RDDIM
Host Display
Send 2nd parameter Dummy Read
Parameter
Display
Action Send 2nd parameter Mode
Sequential transter
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9.1.9 RDDSM: Read Display Signal Mode (0Eh)
A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 D7 D6 0 D6 D5 0 0 D4 0 0 D3 1 0 D2 1 0 D1 1 0 D0 0 0 Hex
(0Eh) -
Command
RDDSM Dummy Read 2nd parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Tearing Effect Line On/Off Tearing effect line mode Horizontal Sync. (RGB I/F) On/Off Vertical Sync. (RGB I/F) On/Off Pixel Clock (DCK, RGB I/F) On/Off Data Enable (ENABLE, RGB I/F) Not Used Not Used Value "1" = On, "0" = Off "0" = mode1, "1" = mode2 "0" (Not Used) "0" (Not Used) "0" (Not Used) "0" (Not Used) "0" "0"
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
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Flow Chart
Serial I/F Mode
Read RDDSM
Parallel I/F Mode
Read RDDSM
Legend
Command
Host Display
Send 2nd parameter Dummy Read
Parameter
Display
Send 2nd parameter
Action
Mode
Sequential transter
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9.1.10 RDDSDR: Read Display Self-Diagnostic Result (0Fh)
Command A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 D7 D6 0 D6 D5 0 D5 D4 0 D4 D3 1 0 D2 1 0 D1 1 0 D0 1 0 Hex
(0Fh) -
RDDSDR Dummy Read 2nd parameter NOTE: "-" Don't care Description
This command indicates the current status of the display as described in the table below:
Bit D7 D6 D5 D4 D3 D2 D1 D0 Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used "0" "0" "0" "0" Value See section 7.10
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D[7:0]) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
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Flow Chart
Serial I/F Mode
Read RDDSDR
Parallel I/F Mode
Read RDDSDR
Legend
Command
Host Display
Parameter Send 2nd parameter Dummy Read Display
Send 2nd parameter
Action
Mode
Sequential transter
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9.1.11 SLPIN: Sleep In (10h)
Command
SLPIN Parameter
A0 0
/RD 1
/WR 0
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
0
Hex
(10h)
No Parameter
Description
This command causes the LCD module to enter the minimum power consumption mode. In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
COM/SEG Output
Memory scan operation
DC charge in the capacitor LCD Driving voltage (Plus) LCD Driving voltage(Minus)
Blank display
STOP (Blank display) STOP
DISCHARGE
0V
0V 0V
Internal Oscillator
STOP
MCU interface and memory are still working and the memory keeps its contents Restriction This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart It takes about 120 msec to get into Sleep In mode (booster off state) after SLPIN command issued. The results of booster off can be check by RDDST (09h) command Bit31.
Legend
SLPIN Stop DC-DC Converte r Command
Display whole blank screen (Automatic No effect to DISP ON/OFF Commands)
Parameter Stop Internal Oscillator
Display
Drain Charge From LCD Panel
Sleep In Mode Action
Mode
Sequential transter
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9.1.12 SLPOUT: Sleep Out (11h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
0
D0
1
Hex
(11h)
SLPOUT Parameter
No Parameter
Description
This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
(If DISPON 29h is set)
COM/SEG Output
Memory scan operation
DC charge in the capacitor LCD Driving voltage (Plus) LCD Driving voltage(Minus) 0V
STOP (Blank display)
Memory Contents
CHARGE
0V 0V
Internal Oscillator
STOP
Restriction
This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. The display module loads all display supplier's factory default values to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if factory default and register values are same when this load is done and when the display module is already Sleep Out -mode. The display module is doing self-diagnostic functions during this 5msec. See also section 7.10. It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent.
Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. The results of booster on can be check by RDDST (09h) command Bit31.
Legend
SLPOUT Display whole blank screen for 2 firames (Automatic No effect to DISP ON/OFF Commands)
Command
Parameter
Start Internal Oscillator
Display
Start up DC:DC Converter Display Memory contents In accordance with the current command table settings
Action
Charge Offset voltage for LCD Panel
Mode
Sleep Out mode
Sequential transter
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9.1.13 PTLON: Partial Display Mode On (12h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
0
Hex
(12h)
PTLON Parameter
No Parameter
Description
This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H) Exit from PTLON by Normal Display Mode On command (13H) There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On.
Restriction Register Availability
This command has no effect when Partial mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Partial mode off Partial mode off Partial mode off
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
See Partial Area (30h)
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9.1.14 NORON: Normal Display Mode On (13h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
1
Hex
(13h)
NORON Parameter
No Parameter
Description
This command returns the display to normal mode. Normal display mode on means Partial mode off, Scroll mode Off. Exit from NORON by the Partial mode On command (12h) There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On.
Restriction Register Availability
This command has no effect when Normal Display mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
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9.1.15 INVOFF: Display Inversion Off (20h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
0
Hex
(20h)
INVOFF Parameter
No Parameter
Description
This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status.
(Example) Memory Display
Restriction Register Availability
This command has no effect when module is already inversion off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Command Display Inversion On Mode
Parameter
Display INVOFF
Action Display Inversion Off Mode Mode
Sequential transter
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9.1.16 INVON: Display Inversion On (21h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
0
D0
1
Hex
(21h)
INVON Parameter
No Parameter
Description
This command is used to enter into display inversion mode This command makes no change of contents of frame memory. This command does not change any other status. To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
(Example) Memory Display
Restriction Register Availability
This command has no effect when module is already Inversion On mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Display Inversion Off Mode Command
Parameter
INVON Display
Display Inversion On Mode
Action
Mode
Sequential transter
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9.1.17 APOFF: All Pixels Off (22h) (Only for Test Purposes)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
1
D0
0
Hex
(22h)
APOFF Parameter
No Parameter
Description
This command is only used for test purpose e.g. pixel response time (on/off) measurements on the passive matrix display. Therefore, it is possible that this command is not used for final product software. All driver outputs become "Low" data state and display becomes black. This command makes no change of contents of display memory. This command does not change any other status. Exit commands are "All Pixels On", "Normal Display Mode On" and "Partial Display On". The display is showing the contents of the frame memory after "Normal Display Mode On" and "Partial Display On" commands.
(Example) Memory Display
Restriction Register Availability
This command has no effect when module is already All Pixel Off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value All pixel off mode disable All pixel off mode disable All pixel off mode disable
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Command Normal Display Mode On
Parameter
Display ALLPOFF
Action All Pixels Off Mode Mode
Sequential transter
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9.1.18 APON: All Pixels On (23h) (Only for Test Purposes)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
0
D3
0
D2
0
D1
1
D0
1
Hex
(23h)
APON Parameter
No Parameter
Description
This command is only used for test purpose e.g. pixel response time (on/off) measurements on the passive matrix display. Therefore, it is possible that this command is not used for final product software. All driver outputs become "High" data state and display becomes white. This command makes no change of contents of display memory. This command does not change any other status. Exit commands are "All Pixels On", "Normal Display Mode On" and "Partial Display On". The display is showing the contents of the frame memory after "Normal Display Mode On" and "Partial Display On" commands.
(Example) Memory Display
Restriction Register Availability
This command has no effect when module is already All Pixel On mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value All pixel on mode disable All pixel on mode disable All pixel on mode disable
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Normal Display Mode On Command
Parameter
ALLPON Display
All Pixels On Mode
Action
Mode
Sequential transter
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9.1.19 WRCNTR: Write Contrast (25h)
Command A0 0 1 /RD 1 1 /WR 0 0 D7
0 -
D6
0 EV6
D5
1 EV5
D4
0 EV4
D3
0 EV3
D2
1 EV2
D1
0 EV1
D0
1 EV0
Hex
(25h)
WRCNTR 1st Parameter
Description
This command is used to fine tuning the contrast of the current display. This contrast values can affect segment and common outputs. Parameter range: 0-127dec. MSB is EV6 and LSB is EV0. Default value: 63dec (3Fh)
Restriction Register Availability
-
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset Default Value 3Fh 3Fh 3Fh
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Flow Chart
Legend
Command
WRCNTR
Parameter
Display EV[7:0]
Action
New Contrast Value Loaded
Mode
Sequential transter
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9.1.20 DISPOFF: Display Off (28h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
0
Hex
(28h)
DISPOFF Parameter
No Parameter
Description
This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. Exit from this command by Display On (29h)
(Example) Memory Display
Restriction Register Availability
This command has no effect when module is already in Display Off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Command
Display On Mode
Parameter
Display
DISPOFF Action
Display Off Mode
Mode
Sequential transter
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9.1.21 DISPON: Display On (29h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
0
D3
1
D2
0
D1
0
D0
1
Hex
(29h)
DISPON Parameter
No Parameter
Description
Turn on the display screen according to the current display data RAM content and the display timing and setting. This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory. This command does not change any other status.
(Example) Memory Display
Restriction Register Availability
This command has no effect when module is already in Display On mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Command
Display Off Mode
Parameter
Display
DISPON Action
Display On Mode
Mode
Sequential transter
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9.1.22 CASET: Column Address Set (2Ah)
Command A0 0 1 1 /RD 1 1 1 /WR 0 0 0 D7 0
-
D6 0
XS6 XE6
D5
1 XS5 XE5
D4 0
XS4 XE4
D3
1 XS3 XE3
D2 0
XS2 XE2
D1
1 XS1 XE1
D0 0
XS0 XE0
Hex
(2Ah)
CASET 1st Parameter 2nd Parameter NOTE: "-" Don't care Description
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of XS [6:0] and XE [6:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
Restriction
XS [6:0] always must be equal to or less than XE [6:0] When XS [6:0] or XE [6:0] is greater than 61h (when MV=0) or 45h (when MV=1), data of out of range will be ignored. (Parameter range: 0 XS [7:0] XE [7:0] 97(61h)) : MV="0" (Parameter range: 0 XS [7:0] XE [7:0] 69(45h)) : MV="1"
Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes Default Value XS [6:0] XE [6:0] (MV=0) XE [6:0] (MV=1)
Default
Status
Power On Sequence S/W Reset H/W Reset
00h (00d) 00h (00d) 00h (00d)
61h (97d) 61h (97d) 61h (97d) 45h (69d)
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Flow Chart
CASET
Legend
1st parameter XS[6:0] 2nd parameter XE[6:0]
Command
Parameter
PASET
Display
1st parameter YS[6:0] 2nd parameter YE[6:0]
Action
RAMWR
Mode
Image Data D1[7:0],D2[7:0] ... ... .Dn[7:0]
Sequential transter
Any Command
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9.1.23 RASET: Row Address Set (2Bh)
Command A0 0 1 1 /RD 1 1 1 /WR 0 0 0 D7 0
-
D6 0
YS6 YE6
D5
1 YS5 YE5
D4 0
YS4 YE4
D3
1 YS3 YE3
D2 0
YS2 YE2
D1
1 YS1 YE1
D0 1
YS0 YE0
Hex
(2Bh)
RASET 1st Parameter 2nd Parameter NOTE: "-" Don't care Description
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of YS [6:0] and YE [6:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
(Example)
YS[6:0]
YE[6:0]
Restriction
YS [6:0] always must be equal to or less than YE [6:0] When YS [6:0] or YE [6:0] is greater than 45h (when MV=0) or 61h (when MV=1), data of out of range will be ignored. (Parameter range: 0YS [6:0] YE [6:0] 69 (45h)) : MV = "0" (Parameter range: 0YS [6:0] YE [6:0] 97 (61h)) : MV = "1"
Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Availability Yes Yes Yes Yes Yes Default Value YS [6:0] YE [6:0] (MV=0) YE [6:0] (MV=1)
Default
Status
Power On Sequence S/W Reset H/W Reset
00h (00d) 00h (00d) 00h (00d)
45h (69d) 45h (69d) 45h (69d) 61h (97d)
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Flow Chart
CASET
Legend
1st parameter XS[6:0] 2nd parameter XE[6:0] Command
Parameter
PASET
Display
1st parameter YS[6:0] 2nd parameter YE[6:0]
Action
Mode RAMWR Sequential transter Image Data D1[7:0],D2[7:0] ... ... .Dn[7:0]
Any Command
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9.1.24 RAMWR: Memory Write (2Ch)
Command A0 0 1 1 1 /RD 1 1 1 1 /WR 0 0 0 0 D7 0
D7
D6 0
D6
D5
1 D5
D4 0
D4
D3
1 D3
D2 1
D2
D1
0 D1
D0 0
D0
Hex
(2Ch) -
RAMWR Write Data 1 D1[7:0] : Write Data n Dn[7:0]
:
D7
:
D6
:
D5
:
D4
:
D3
:
D2
:
D1
:
D0
-
Description
This command is used to transfer data MCU to frame memory. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTR setting. Then D [7:0] is stored in frame memory and the column register and the row register incremented as in Figure 7.3. Frame Write can be canceled by sending any other command.
Restriction Register Availability
In all color modes, there is no restriction on length of parameters.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is remained Contents of memory is remained
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
Command
RAMWR Parameter
Display Image Data D1[7:0],D2[7:0] ... ... .Dn[7:0]
Action
Mode
Any Command
Sequential transter
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9.1.25 RGBSET: Color Set for 256-Color Display (2Dh)
Command A0 0 1 1 1 1 1 1 1 1 1 /RD 1 1 1 1 1 1 1 1 1 1 /WR 0 0 0 0 0 0 0 0 0 0
0 : : : -
D7
0 : : : -
D6
1 : -
D5
0
D4
1
D3
1
D2
0
D1
1
D0
Hex
(2Dh) -
RGBSET 1st parameter : 16th parameter 17th parameter : 32nd parameter 33rd parameter : 48th parameter NOTE: "-" Don't care Description
R004 Rnn4 R154 G004 Gnn4 G154 B004 Bnn4 B154
R003 Rnn3 R153 G003 Gnn3 G153 B003 Bnn3 B153
R002 Rnn2 R152 G002 Gnn2 G152 B002 Bnn2 B152
R001 Rnn1 R151 G001 Gnn1 G151 B001 Bnn1 B151
R000 Rnn0 R150 G000 Gnn0 G150 B000 Bnn0 B150
G005 Gnn5 G155 : -
This command is used to define the LUT for 8bit-to-16bit or 12bit-to-16bit color depth conversations. (See also Section 7.8) 48 Bytes must be written to the LUT regardless of the color mode. Only the values in Section 7.8 are referred. This command has no effect on other commands/parameters and Contents of frame memory. Visible change takes effect next time the Frame Memory is written to.
Restriction Register Availability
Do not send any command before the last data is sent or LUT is not defined correctly.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Refer to Section 7.8 Contents of the look-up table protected Refer to Section 7.8
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
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9.1.26 RAMRD : Memeory Read (2EH)
Command A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 0 x
D7
D6 0 x
D6
D5
1 x D5
D4 0 x
D4
D3
1 x D3
D2 1 x
D2
D1
0 x D1
D0 0 x
D0
Hex
(2Eh) x 00H ~ FFH
RAMRD Dummy Read Read Data 1 D1[7:0] ... Read Data n Dn[7:0]
1
0
1
Dn7
Dn6
Dn5
Dn4
Dn3
Dn2
Dn1
Dn0
00H ~ FFH
Description
This command is used to transfer data from frame memory to MCU. When this command is accepted, the column register and the page register are reset to the Start Column/Start Page positions. The Start Column/Start Page positions are different in accordance with MADCTR setting. Then D[7:0] is read back from the frame memory and the column register and the page register incremented. Frame Read can be stopped by sending any other command.
Restriction Register Availability
Memory Read is only possible via the Parallel Interface.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In or Booster Off
Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
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Flow Chart
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9.1.27 PTLAR: Partial Area (30h)
Command A0 0 1 1 /RD 1 1 1 /WR 0 0 0 D7
0 -
D6
0 PS6 PE6
D5
1 PS5 PE5
D4
1 PS4 PE4
D3
0 PS3 PE3
D2
0 PS2 PE2
D1
0 PS1 PE1
D0
0 PS0 PE0
Hex
(30h) -
PTLAR 1st Parameter 2nd Parameter NOTE: "-" Don't care Descriptio n
This command defines the partial mode's display area. There are 2 parameters associated with this command, the first defines the Start Line (PSL) and the second the End Line (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory Line counter. If End Line > Start Line when MADCTR ML=0:
If End Line > Start Line when MADCTR ML=1:
If End Line < Start Line when MADCTR ML=0:
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* Row1: Frame memory row address 1. If End Line = Start Line then the Partial Area will be one line deep. Restriction PSL[6:0] and PEL[6:0] is based on line unit. PSL[6:0]=00h, 01h, 02h, 03h, ... , 45h PEL[6:0]= 00h, 01h, 02h, 03h, ... , 45h Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value PSL [6:0] Power On Sequence S/W Reset H/W Reset 00h (00d) 00h (00d) 00h (00d) PEL [6:0] 45h (69d) 45h (69d) 45h (69d)
Default
Status
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9.1.28 SCRLAR: Scroll Area (33h)
Command A0 0 1 1 1 /RD 1 1 1 1 /WR 0 0 0 0 D7
0 -
D6
0 TFA6 VSA6 BFA6
D5
1 TFA5 VSA5 BFA5
D4
1 TFA4 VSA4 BFA4
D3
0 TFA3 VSA3 BFA3
D2
0 TFA2 VSA2 BFA2
D1
1 TFA1 VSA1 BFA1
D0
1 TFA0 VSA0 BFA0
Hex
(33h) -
SCRLAR 1st parameter 2nd parameter 3rd parameter NOTE: "-" Don't care Descriptio n
This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll. When MADCTR BL=0 The 1st parameter TFA [6:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). The 2nd parameter VSA [6:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. The 3rd parameter BFA [6:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer.
Restriction
The condition is (TFA+VSA+BFA) = 70, otherwise Scrolling mode is undefined. In Vertical Scroll Mode, MADCTR parameter MV should be set to `0'-this only affects the Frame Memory Write. TFA[6:0], VSA[6:0] and BFA[6:0] is based on line unit. TFA[6:0]= 00h, 01h, 02h, 03h, ... , 46h VSA[6:0]= 00h, 01h, 02h, 03h, ... , 46h BFA[6:0]= 00h, 01h, 02h, 03h, ... , 46h
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Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value TFA [6:0] Power On Sequence S/W Reset H/W Reset 00h 00h 00h VSA [6:0] 46h (70d) 46h (70d) 46h (70d) BFA [6:0] 00h 00h 00h
Default
Status
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Flow Chart
1. TO Enter Vertical Scroll Mode:
Normal Mode
SCRLAR 1st parameter TFA[6:0] 2nd parameter VSA[6:0] 3rd parameter BFA[6:0]
Legend
Command
Parameter
CASET Display 1st parameter XS[6:0] 2nd parameter XE[6:0]
RASET
Only required for non-rolling scrolling
1st parameter YS[6:0] 2nd parameter YE[6:0]
Redefines the Frame Memory Window that the scroll data will be written to. Optional - It may be necessary to redefine the frame memory write direction.
Action
Mode
MADCTR Parameter
Sequential transter
RAMWR
Scroll Video Data
VSCSAD 1st parameter SSA[6:0] Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
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Flow Chart
2. Continuous Scroll:
Normal Mode
CASET 1st parameter XS[6:0] 2nd parameter XE[6:0]
Legend
Command
Parameter
Only required for non-rolling scrolling
RASET 1st parameter YS[6:0] Display 2nd parameter YE[6:0]
RAMWR
Action
Scroll Video Data Mode VSCSAD 1st parameter SSA[6:0] Sequential transter
3. To Exit Vertical Scroll Mode:
Scroll Mode Can be skipped
DISPOFF NORON/PTLON Scroll Mode OFF
RAMWR
Video Data D1[7:0], D2[7:0]...Dn[7:0]
DISPON
NOTE: Scroll Mode can be exit by both the Normal Display Mode On(13h) and Partial Mode On (12h) commands.
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9.1.29 TEOFF: Tearing Effect Line OFF (34h)
Command
TEOFF
A0 0
/RD 1
/WR 0
D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
0
D0
0
Hex
(34h)
Parameter
No Parameter
Description
This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction Register Availability
This command has no effect when Tearing Effect output is already OFF.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Tearing effect off Tearing effect off Tearing effect off
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
Legend
Command TE Line Output ON Parameter
TEOFF
Display
TE Line Output OFF
Action
Mode
Sequential transter
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9.1.30 TEON: Tearing Effect Line ON (35h)
Command
TEON
A0 0 1
/RD 1 1
/WR 0 0
D7
0 -
D6
0 -
D5
1 -
D4
1 -
D3
0 -
D2
1 -
D1
0 -
D0
1 M
Hex
(35h)
Parameter NOTE: "-" Don't care Descriptio n
This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTR bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. ("-"=Don't Care). When M=0: The Tearing Effect Output Line consists of V-Blanking information only:
When M=1: The Tearing Effect Output Line consists of both V-Blanking and H-Blanking information:
See section 7.3.8 for more information.
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Restriction Register Availability This command has no effect when Tearing Effect output is already OFF.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Tearing effect off & M=0 Tearing effect off & M=0 Tearing effect off & M=0
Default
Status Power On Sequence S/W Reset H/W Reset
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9.1.31 MADCTR: Memory Data Access Control (36h)
Command A0 0 1 /RD 1 1 /WR 0 0 D7
0
D6
0
D5
1
D4
1
D3
0
D2
1
D1
1
D0
0
Hex
(36h) -
MADCTR Parameter NOTE: "-" Don't care Description
MY
MX
MV
ML
RGB
-
-
-
This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Note: ML affects to Partial Area (30h), Vertical Scrolling Definition (33h), Vertical Scrolling Start address (37h), Partial On (12h) commands Bit Assignment
Bit MY MX MV ML RGB NAME ROW ADDRESS ORDER COLUMN ADDRESS ORDER ROW/COLUMN ORDER LINE ADDRESS ORDER RGB-BGR ORDER LCD refresh direction control Color selector switch control 0=RGB color filter panel, 1=BGR color filter panel) The contents of the frame memory are not changed. DESCRIPTION These 3bits controls MCU to memory write/read direction. (See Section 7.3.2 "MCU to memory write/read direction")
Restriction Register Availability
D2, D1 and D0 of the 1st parameter are set to `000'internally.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes
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Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Yes Yes Yes Yes Default Value MY=0,MX=0,MV=0,ML=0,RGB=0 Not changed MY=0,MX=0,MV=0,ML=0,RGB=0
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
Legend
Command MADCTL Parameter
Display
1st parameter B[7:0]
Action
Mode
Sequential transter
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9.1.32 VSCSAD: Vertical Scroll Start Address of RAM (37h)
Command A0 0 1 /RD 1 1 /WR 0 0 D7
0 -
D6
0 SSA6
D5
1 SSA5
D4
1 SSA4
D3
0 SSA3
D2
1 SSA2
D1
1 SSA1
D0
1 SSA0
Hex
(37h)
VSCSAD Parameter NOTE: "-" Don't care
Description
This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: This command Start the scrolling. Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. SSA refers to the Frame Memory line Pointer Restriction Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel.
SSA [6:0] is based on line unit. SSA [6:0] = 00h, 01h, 02h, 03h, ... , 45h
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Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes No No Yes Default Value 00 00 00
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
See Vertical Scrolling Definition (33h) description.
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9.1.33 IDMOFF: Idle Mode Off (38h)
Command A0 0 /RD 1 /WR 0 D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0
0
Hex
(38h)
IDMOFF Parameter
No Parameter
Description
This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle off mode, 1. LCD can display maximum 65536 colors. 2. Normal frame frequency is applied.
Restriction Register Availability
This command has no effect when module is already in idle off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Idle mode off Idle mode off Idle mode off
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.34 IDMON: Idle Mode On (39h)
Command
IDMON
A0 0
/RD 1
/WR 0
D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0
1
Hex
(39h)
Parameter
No Parameter
Description
This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R, G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command
"X": don't care Color Black Blue Red Magenta Green Cyan Yellow White R4 R3 R2 R1 R0 0XXXX 0XXXX 1XXXX 1XXXX 0XXXX 0XXXX 1XXXX 1XXXX G5 G4 G3 G2 G1 G0 0XXXXX 0XXXXX 0XXXXX 0XXXXX 1XXXXX 1XXXXX 1XXXXX 1XXXXX B4 B3 B2 B1 B0 0XXXX 1XXXX 0XXXX 1XXXX 0XXXX 1XXXX 0XXXX 1XXXX
Restriction Register Availability
This command has no effect when module is already in idle on mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value
Default
Status
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Power On Sequence S/W Reset H/W Reset Idle mode off Idle mode off Idle mode off
Flow Chart
Legend
Command Idle off mode Parameter
IDMON
Display
Idle on mode
Action
Mode
Sequential transter
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9.1.35 COLMOD: Interface Pixel Format (3Ah)
Command A0 0 1 /RD 1 1 /WR 0 0 D7
0
D6
0
D5
1
D4
1
D3
1
D2
0
D1
1
D0
0
Hex
(3Ah) -
COLMOD Parameter
-
-
-
-
-
P2
P1
P0
Description
This command is used to define the format of RGB picture data, which is to be transferred via the MCU Interface. The formats are shown in the table:
Interface Format Not Defined Not Defined 8Bit/Pixel 12Bit/Pixel (Type A) 12Bit/Pixel (Type B) 16Bit/Pixel 18Bit/Pixel 24Bit/Pixel P2 0 0 0 0 1 1 1 1 P1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1
Note: In 8 bit/pixel or 12 bit/pixel mode, the LUT is applied to transfer data into the Frame Memory. Restriction Register Availability There is no visible effect until the Frame Memory is written to.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 05h (16Bit/Pixel) No Change 05h (16Bit/Pixel)
Default
Status Power On Sequence S/W Reset H/W Reset
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Flow Chart
Legend
16 Bit/Pixel Mode Command
Parameter COLMOD Display
011
Action
Mode 12 Bit/Pixel Mode Sequential transter
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9.1.36 RDID1: Read ID1 Value (DAh)
Command A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7
1
D6
1
D5
0
D4
1
D3
1
D2
0
D1
1
D0
0
Hex
(DAh) -
RDID1 Dummy Read 2nd parameter NOTE: "-" Don't care Description
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
This read byte returns 8-bit LCD module's manufacturer ID D7-D0 (ID17 to ID10): LCD module's manufacturer ID. NOTE: See command RDDID (04h), 2nd parameter.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 45h 45h 45h
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.37 RDID2: Read ID2 Value (DBh)
Command A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7
1
D6
1
D5
0
D4
1
D3
1
D2
0
D1
1
D0
1
Hex
(DBh) -
RDID2 Dummy Read 2nd parameter NOTE: "-" Don't care Description
ID27
ID26
ID25
ID24
ID23
ID22
ID21
ID20
This read byte returns 8-bit LCD module/driver version ID D7-D0 (ID27 to ID20): LCD module/driver version ID Parameter Range: ID=80h to FFh NOTE: See command RDDID (04h), 3rd parameter.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value[6:0] D2h D2h D2h
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.38 RDID3: Read ID3 Value (DCh)
Command A0 0 1 1 /RD 1 0 0 /WR 0 1 1
1
D7
1
D6
0
D5
1
D4
1
D3
1
D2
0
D1
0
D0
Hex
(DCh)
RDID3 Dummy Read 2nd parameter NOTE: "-" Don't care Description
ID37
ID36
ID35
ID34
ID33
ID32
ID31
-
-
ID30 -
This read byte returns 8-bit LCD module/driver ID. D7-D0 (ID37 to ID30): LCD module/driver ID. NOTE: See command RDDID (04h), 4th parameter.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 0Eh 0Eh 0Eh
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.39 DutySet: Display Duty setting (B0H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 0 D6 0 Du6 D5 1 Du5 D4 1 Du4 D3 0 Du3 D2 0 Du2 D1 0 Du1 D0 0 Du0 Hex
(B0h)
DutySet Parameter NOTE: "-" Don't care Description
This command is used to set display duty. Command set = display duty numbers - 1. Example: Command set= Duty Du6 Du5 Du4 Du3 Du2 Du1 Du0 Display duty numbers-1 Example: 1 1/70 duty 0 0 0 1 0 1 70-1=69
Restriction Register Availability
Display duty must > 4 (1/4 duty) Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 01000101b (45h) 01000101b (45h) 01000101b (45h) (Du[6:0])
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.40 FirstCom: First Com. Page address (B1H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 -D6 0 F6 D5 1 F5 D4 1 F4 D3 0 F3 D2 0 F2 D1 0 F1 D0 1 F0 Hex
(B1h)
FirstCom Parameter NOTE: "-" Don't care Description
-
This command defines the first output COM number that mapping to the RAM page address 0. For detail setting value, please see the table as below.
F6 0 0 0 0 : 1 F5 0 0 0 0 : 0 F4 0 0 0 0 : 0 F3 0 0 1 1 : 0 F2 F1 F0 0 1 0 1 : 1 Line address 0 1 2 3 : 69
1
0
Example: If FirstCom=8, common 8 would output the data of RAM page address 0.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 00h 00h 00h (F[6:0])
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.41 OscDiv: FOSC Divider (B3H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 D1 1 D0 1 Hex
(B3h)
OscDiv Parameter NOTE: "-" Don't care Description
CLD1 CLD0
-
This command is used to specify the Fosc dividing ratio. CLD1, CLD0: Fosc dividing ratio. They are used to change number of dividing stages of external or internal clock.
CLD1 0 0 1 1
CLD0 0 1 0 1
Fosc dividing ratio Not divide 2 divisions 4 divisions 8 divisions
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 00b 00b 00b (CLD[0:1])
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.42 PTLMOD: Partial Saving Power Mode Selection (B4H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 PTLM D6 0 0 D5 1 0 D4 1 1 D3 0 1 D2 1 0 D1 0 0 D0 0 0 Hex
(B4h)
OscDiv Parameter NOTE: "-" Don't care Description
-
Two type partial modes are built in ST7628. One is NORMAL MODE(PTLM=0) and another is POWER SAVING MODE(PTML=1). When entering power saving mode, IC would change bias, V0, booster pumping times in 4 special partial lines in order to save power consumptions, please see the following table: Duty 24 32 40 48 Bias 1/6 1/6 1/6 1/6 Bst pump 5x 5x 5x 5x V0(V) 9+(Vopoffset/2) 9.68+(Vopoffset/2) 10.12+(Vopoffset/2) 10.52+(Vopoffset/2)
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 18h 18h 18h
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.43 NLInvSet: N-Line control (B5H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 M D6 0 N6 D5 1 N5 D4 1 N4 D3 0 N3 D2 1 N2 D1 0 N1 D0 1 N0
-
Hex
(B5h)
NLInvSet Parameter NOTE: "-" Don't care Description
This command is used to set the inverted line number with range of 2 to (duty-1) to improve display quality. When M=0, inversion occurs in every frame; when M=1, inversion is independent from frames. If N[6:0]=0, N-line inversion function is disable. Line inversion numbers=N[6:0] +1. Example: If N[6:0]=7, inversion occurs per 8 line.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Default Value M Power On Sequence S/W Reset H/W Reset 0b 0b 0b N[6:0] 0000000b 0000000b 0000000b
Flow Chart
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9.1.44 ComScanDir: Com/Seg Scan Direction for glass layout(B7H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 SMY D6 0 SMX D5 1 SINV D4 1 D3 0 D2 1 D1 1 D0 1 Hex
(B7h) -
ComScanDir Parameter NOTE: "-" Don't care Description
SML SBGR
Function SMY SMX SINV SML SBGR Inverse the MY setting Inverse the MX setting Inverse the INVON setting Inverse the ML setting Inverse the BGR setting
0 Keep MY Keep MX Keep INVON Keep ML Keep BGR
1 Inverse MY Inverse MX Inverse INVON Inverse ML Inverse BGR
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 49h 49h 49h
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.45 RMWIN: Read Modify Write control in(B8H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 Hex
(B8h)
RMWIN Parameter
No Parameter
NOTE: "-" Don't care Description Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value ---
Read modify write control IN
Default
Status Power On Sequence S/W Reset H/W Reset
--
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9.1.46 RMWOUT: Read Modify Write control out(B9H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 Hex
(B9h)
RMWOUT Parameter
No Parameter
NOTE: "-" Don't care Description Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value ---
Read modify write control OUT
Default
Status Power On Sequence S/W Reset H/W Reset
--
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9.1.47 VopSet: Vop set (C0H)
Command A0 0 1 1 /RD 1 1 1 /WR 0 0 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 Hex
(C0h)
VopSet 1 parameter
st
Vop7 Vop6 Vop5 Vop4 Vop3 Vop2 Vop1 Vop0 Vop8
2 parameter
NOTE: "-" Don't care Description Restriction Register Availability
Status
nd
The command is used to program the optimum LCD supply voltage V0.
Availability Yes Yes Yes Yes Yes Default Value (Vop=12V) Vop8 Vop[7:0] 11010010b (D2h) 11010010b (D2h) 11010010b (D2h)
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status
Power On Sequence S/W Reset H/W Reset
0 0 0
Flow Chart
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9.1.48 VopOfsetInc: Vop Increase 1 (C1H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 Hex
(C1h)
VopOfsetInc NOTE: "-" Don't care Description
With the VopOfsetInc and VopOfsetDec command the V0 voltage and therewith the contrast of the LCD can be adjusted. This command increases the value of Vop offset register by 1.
If you set the electronic control value to 1111111, the control value is set to 0000000 after this command has been executed.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value ---
Default
Status Power On Sequence S/W Reset H/W Reset
--
Flow Chart
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9.1.49 VopOfsetDec: Vop Decrease 1 (C2H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0 Hex
(C2h)
VopOfsetDec NOTE: "-" Don't care Description
With the VopOfsetInc and VopOfsetDec command the V0 voltage and therewith the contrast of the LCD can be adjusted. This command decreases the value of Vop offset register by 1.
If you set the electronic control value to 0000000, the control value is set to 1111111 after this command has been executed.
Electronic Control Value
Decimal Equivalent 63 62 61 ... 2 1 0 -1 -2 ... -62 -63 -64
V0 Offset
0111111
0111110 0111101 ...
+2520 mV +2480 mV +2440 mV ... +80 mV +40 mV 0 mV -40 mV -80 mV ... -2480 mV -2520 mV -2560mV
0000010 0000001 0000000
1111111
1111110
...
1000010
1000001 1000000
Table 9.1.1
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Possible Vop[6:0] values
Availability Yes Yes Yes Yes Yes Default Value ---
Default
Status Power On Sequence S/W Reset H/W Reset
--
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Flow Chart
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9.1.50 BiasSel: Bias Selection(C3H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 Hex
(C3h)
BiasSel Parameter NOTE: "-" Don't care Description
Bias2 Bias1 Bias0
-
Select LCD bias ratio of the voltage required for driving the LCD. Bais2 0 0 0 0 1 1 1 1 Bais1 0 0 1 1 0 0 1 1 Bais0 0 1 0 1 0 1 0 1 LCD bias 1/12 1/11 1/10 1/9 1/8 1/7 1/6 1/5
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 010b 010b 010b (Bias[2:0])
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.51 BstPmpXSel: Booster Set(C4H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0 Hex
(C4h)
BstPmpXSel Parameter NOTE: "-" Don't care Description
BST2 BST 1 BST0 -
Booster setting
BST2 0 0 0 0 1 1 1 1 BST1 0 0 1 1 0 0 1 1 BST0 x1 boosting circuit 0 (Booster off) 1 0 1 0 1 0 1 x2 boosting circuit x3 boosting circuit x4 boosting circuit x5 boosting circuit x6 boosting circuit x7 boosting circuit x8 boosting circuit
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset Default Value 111b 111b 111b (BST[2:0])
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Flow Chart
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9.1.52 BstEffSel: Booster Efficiency selection(C5H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 0 1 D4 0 0 D3 0 D2 1 D1 0 D0 1 Hex
(C5h)
BstEffSel Parameter NOTE: "-" Don't care Description
BTF1 BTF0 -
Booster Efficiency set BTF1 0 0 1 BTF0 0 1 0 Frequency Level 1 Level 2 (default) Level 3
By Booster Stages (2X, 3X, 4X, 5X, 6X, 7X, 8X) and Booster Efficiency (Level1~3) commands, we could easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to higher level (level3 is higher than level1). The Boost Efficiency is better than lower level, and it just need few more power consumption current.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default
Status Power On Sequence S/W Reset H/W Reset Default Value (BTF[1:0]) 00100001b (21h) 00100001b (21h) 00100001b (21h)
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Flow Chart
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9.1.53 VopOffset: Vop offset fuse bit adjust(C7H)
Command A0 0 1 1 /RD 1 1 1 /WR 0 0 0 D7 1 D6 1 D5 0 D4 0 D3 0 D2 1 D1 1 D0 1 Hex
(C7h) -
VopOffset Parameter1 Parameter2
VOS7 VOS6 VOS5 VOS4 VOS3 VOS2 VOS1 VOS0 VOS8
NOTE: "-" Don't care Description The command is used to the Vop offset for V0.
Vop offset Control Value
Decimal Equivalent
V0 Offset
... 000000010 000000001 000000000 111111111 111111110 ... Restriction Register Availability
Status
... 2 1 0 -1 2 ...
... +80mV +40mV 0 -40mV -80mV ...
Availability Yes Yes Yes Yes Yes Default Value VOS8 VOS[7:0] 00h 00h 00h
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status
Power On Sequence S/W Reset H/W Reset
0h 0h 0h
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9.1.54 V3SorcSel: FV3 with Bst2x control(CBH)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 0 D1 1 D0 1 2BT0 Hex
(CBh)
V3SorcSel Parameter NOTE: "-" Don't care Description
2BT0=0: Vg source comes from VDD2 ; 2BT0=1: Vg source comes from 2-times charge pump.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value (2BT0) 01h 01h 01h
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.55 ID1Set : ID1 setting(CCH)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0 Hex
(CCh) -
ID1Set Parameter
ID1_7 ID1_6 ID1_5 ID1_4 ID1_3 ID1_2 ID1_1 ID1_0
NOTE: "-" Don't care Description Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 45h 45h 45h ID1 setting for OTP program data input
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.56 ID2Set : ID2 setting(CDH)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 1 Hex
(CDh) -
ID2Set Parameter NOTE: "-" Don't care Description Restriction Register Availability
Status
ID2_6 ID2_5 ID2_4 ID2_3 ID2_2 ID2_1 ID2_0
ID2 setting for OTP program data input
Availability Yes Yes Yes Yes Yes Default Value D2h D2h D2h
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.57 ID3Set : ID3 setting(CEH)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0 Hex
(CEh) -
ID3Set Parameter NOTE: "-" Don't care Description Restriction Register Availability
Status
ID3_7 ID3_6 ID3_5 ID3_4 ID3_3 ID3_2 ID3_1 ID3_0
ID3 setting for OTP program data input
Availability Yes Yes Yes Yes Yes Default Value 0Eh 0Eh 0Eh
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.58 ANASET: Analog circuit setting(D0H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 0 D6 1 0 D5 0 0 D4 1 1 D3 0 1 D2 0 1 D1 0 0 D0 0 1 Hex
(D0h) -
AutoLoadSet Parameter
NOTE: "-" Don't care Description Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value D[7:0] 1Dh 1Dh 1Dh Analog circuit setting. Such as follower selection, level shifter power mode selection.
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.59 AutoLoadSet : mask rom data auto re-load control(D7H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 EXTE D6 1
OTPBE
D5 0 0
D4 1 ARD
D3 0 1
D2 1 1
D1 1 1
D0 1 1
Hex
(D7h) -
AutoLoadSet Parameter
NOTE: "-" Don't care Description
Mask rom data auto re-load control EXTE : External command enable (OTP bit), 1: enable, 0: disable. OTPBE: OTPB auto-read enable (OTP bit) , 1: enable, 0: disable. ARD : OTP auto-read enable control, 1: Disable OTP auto-read, 0: Enable OTP auto-read
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default ValueD[7:0] 00h 00h 00h
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.60 RDTstStatus : Read IC status(DEH)
Command A0 0 1 1 /RD 1 0 0 /WR 0 1 1 D7 1 RD7 D6 1 RD6 D5 0 RD5 D4 1 RD4 D3 1 RD3 D2 1 RD2 D1 1 RD1 D0 0 RD0
-
Hex
(DEh)
RDTstStatus Dummy Read Parameter NOTE: "-" Don't care Description
Read IC status. Contect of OTP / RDA / PWR_VOP read control (selection Byte by StusRDSEL[3:0] control)
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value -
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.61 EPCTIN: Control OTP WR/RD(E0H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 0 D6 1 0 /XRD D5 1 WR D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 Hex
(E0h) -
EPCTIN Parameter
NOTE: "-" Don't care Description
WR/XRD: when setting "1" WR/XRD: when setting "0"
The Write Enable of OTP will be opened. The Read Enable of OTP will be opened.
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 0 0 0 (WR/XRD)
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.62 EPCOUT: OTP control cancel(E1H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Hex
(E1h)
EPCOUT NOTE: "-" Don't care Description Restriction Register Availability
Status
IC exits the OTP control circuit when executing this command.
Availability Yes Yes Yes Yes Yes Default Value ---
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status Power On Sequence S/W Reset H/W Reset
--
Flow Chart
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9.1.63 EPMWR: Write to OTP(E2H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Hex
(E2h)
EPCOUT NOTE: "-" Don't care Description Restriction Register Availability
Status
IC actives trigger to start OTP programming when executing this command.
Availability Yes Yes Yes Yes Yes Default Value ---
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status Power On Sequence S/W Reset H/W Reset
--
Flow Chart
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9.1.64 EPMRD: Read from OTP(E3H)
Command A0 0 /RD 1 /WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Hex
(E3h)
EPMRD NOTE: "-" Don't care Description Restriction Register Availability
Status
IC actives trigger to start OTP data download to circuit when executing this command.
Availability Yes Yes Yes Yes Yes Default Value
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.65 OTPSEL: SEL OTP(E4H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 MS1 D6 1 MS0 D5 1 0 D4 0 1 D3 0 1 D2 1 0 D1 0 0 D0 0 0 Hex
(E4h)
OTPSEL Parameter NOTE: "-" Don't care Description
-
This command defines OTP/ OTPB selection for EEPROM control. Please see the table as below:
MS1 0 0 1
MS0 0 1 1
Mode Disable OTP OTPB
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 00 00 00 (MS[1:0])
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.66 ROMSET: Programmable rom setting(E5H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 0 0 D6 1 0 D5 1 0 D4 1 0 D3 0 1 D2 1 0 D1 0 0 D0 1 1 Hex
(E5h) -
AutoLoadSet Parameter
NOTE: "-" Don't care Description Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value D[7:0] 0Fh 0Fh 0Fh Set the OTP writing timing. Value 0x09 is the best value for ST7628.
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.67 StusRDSel : Fuse data readout control(E6H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 Hex
(E6h) -
StusRDSel Parameter NOTE: "-" Don't care Description
STU3 STU2 STU1 STU0
Status read out byte selection STU[3:0] = 0h-3h: OTP.D[7:0], D[15:8], D[23:16], D[31:24], 4h-7h: Dummy data 8h-Bh: OTPB.D[7:0], D[15:8], D[23:16], D[31:24],
Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value 0 0 0
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.68 FRMSEL: Frame Freq. in Temp. range (F0H)
A0 Command 1 parameter 2
nd rd th st
RD 1 1 1 1 1
WR 0 0 0 0 0
D7 1 -
D6 1 -
D5 1 -
D4 1 FA4 FB4 FC4 FD4
D3 0 FA3 FB3 FC3 FD3
D2 0 FA2 FB2 FC2 FD2
D1 0 FA1 FB1 FC1 FD1
D0 0 FA0 FB0 FC0 FD0
HEX F0H Range A Range B Range C Range D
0 1 1 1 1
parameter
3 parameter 4 parameter
Description
Select Frame Freq. in normal display mode. 1 parameter : Frame freq. value set in temperature range 30(-30) to TA 2
nd rd th st
parameter : Frame freq. value set in temperature P range TA to TB
3 parameter : Frame freq. value set in temperature range TB to TC 4 parameter : Frame freq. value set in temperature range TC to 145(90) For command setting to frame rate value look-up-table, please see the following table:
Reg(dec) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Reg(hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
Frame Rate (Hz) 37.5 38 38.5 40 42 44 46 48.5 51 54 57.5 61.5 66.5 72 77.5 85 75 76 77 80 84
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21 22 23 24 25 26 27 28 29 30 31
Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
15 16 17 18 19 1A 1B 1C 1D 1E 1F
88 92 97 102 108 115 123 133 144 155 170
Default Status FA[4:0] Power On Sequence S/W Reset H/W Reset 06h 06h 06h Default Value FB[4:0] 0Bh 0Bh 0Bh FC[4:0] 12h 12h 12h FD[4:0] 14h 14h 14h
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9.1.69 FRM8SEL: Frame Freq. in Temp. range (idel-8 color) (F1H)
A0 Command 1 parameter 2
nd rd th st
RD 1 1 1 1 1
WR 0 0 0 0 0
D7 1 -
D6 1 -
D5 1 -
D4 1
D3 0
D2 0
D1 0
D0 1
HEX F1H Range A Range B Range C Range D
0 1 1 1 1
F8A4 F8A3 F8A2 F8A1 F8A0 F8B4 F8B3 F8B2 F8B1 F8B0 F8C4 F8C3 F8C2 F8C1 F8C0 F8D4 F8D3 F8D2 F8D1 F8D0
parameter
3 parameter 4 parameter
Description
Select Frame Freq. in normal display mode.(idle;8 color mode) 1 parameter : Frame freq. value set in TEMP range 30(-30) to TA 2
nd rd th st
parameter : Frame freq. value set in TEMP range TA to TB
3 parameter : Frame freq. value set in TEMP range TB to TC 4 parameter : Frame freq. value set in TEMP range TC to 145(90) Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Default Status FA[4:0] Power On Sequence S/W Reset H/W Reset 06h 06h 06h Default Value FB[4:0] 0Bh 0Bh 0Bh FC[4:0] 12h 12h 12h FD[4:0] 14h 14h 14h
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Flow Chart
FRM8SL
1st parameter. F8A[4:0] 2nd parameter. F8B[4:0] 3rd parameter. F8C[4:0] 4th parameter. F8D[4:0]
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9.1.70 TMPRNG: Temp. range set for Frame Freq. Adj. (F2H)
A0 Command 1 parameter 2
nd rd st
RD 1 1 1 1
WR 0 0 0 0
D7 1 -
D6 1 TA6 TB6 TC6
D5 1 TA5 TB5 TC5
D4 1 TA4 TB4 TC4
D3 0 TA3 TB3 TC3
D2 0 TA2 TB2 TC2
D1 1 TA1 TB1 TC1
D0 0 TA0 TB0 TC0
HEX F2H Range A Range B Range C
0 1 1 1
parameter
3 parameter
Description
Temp. range set for automatic frame freq. adj. operation according the current temp. value. 1 parameter: Temp. range A value set 2
nd rd st
parameter: Temp. range B value set
3 parameter: Temp. range C value set TA/TB/TC Temperature() + 40 = TA/TB/TC[6:0] Example: If TA wants to be set at 24, TA[6:0]=24+40=64(40h), Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes -40TATA+THTBTB+THTC87
Default Status TA[6:0] Power On Sequence S/W Reset H/W Reset 18h 18h 18h Default Value TB[6:0] 28h 28h 28h TC[6:0] 58h 58h 58h
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Flow Chart
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9.1.71 TMPHYS: Temp.Hysteresis Set for Frame Freq. Adj.(F3H)
A0 Command 1 parameter
st
RD 1 1
WR 0 0
D7 1 -
D6 1 -
D5 1 -
D4 1 -
D3 0 TH3
D2 0 TH2
D1 1 TH1
D0 1 TH0
HEX F3H
0 1
Description
Temp. hysteresis range set for frame freq. adj. Parameter TH[3:0] is used to set Temp. hysteresis range. The relationship between temp. state and temp. range value is shown below.
TEMP Range Value Freq. changing point A Freq. changing point B Freq. changing point C
TEMP Rising State TA[6:0]+TH[3:0] TB[6:0]+TH[3:0] TC[6:0]+TH[3:0]
TEMP Falling State TA[6:0] TB[6:0] TC[6:0]
TH Temperature() - 1 = TH[3:0] Example: If TH wants to set 5, TH[3:0]=5-1=4. Restriction Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Temp. hysteresis value should be smaller than the gap of temp. range.
Default Status Power On Sequence S/W Reset H/W Reset Default Value(TH[3:0]) 04h 04h 04h
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9.1.72 TEMPSEL: Temp. Set(F4H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0
o o
Hex
(F4h)
TEMPSEL 1
st
(-24 C to -32 C)
o o
parameter
MT13 MT12 MT11 MT10 MT03 MT02 MT01 MT00
(-32 C to -40 C)
2
nd
(-8 C to -16 C)
o
o
parameter
1
1
0
MT33 MT32 MT31 MT30 MT23 MT22 MT21 MT20
(-16 C to -24 C)
o o
o
3rd
(8 C to 0 C)
o
parameter
1
1
0
MT53 MT52 MT51 MT50 MT43 MT42 MT41 MT40
(0 C to -8 C)
o
o
4th
(24 C to16 C)
o
o
parameter
1
1
0
MT73 MT72 MT71 MT70 MT63 MT62 MT61 MT60
(16 C to 8 C)
o
o
5th
(40 C to 32 C)
o o o o o o o o
o o o o o o o o
parameter
1
1
0
MT93 MT92 MT91 MT90 MT83 MT82 MT81 MT80
(32 C to 24 C)
6th
(56 C to 48 C)
parameter
1
1
0
MTB3 MTB2 MTB1 MTB0 MTA3 MTA2 MTA1 MTA0
(48 C to 40 C)
7th
(72 C to 64 C)
parameter
1
1
0
MTD3 MTD2 MTD1 MTD0 MTC3 MTC2 MTC1 MTC0
(64 C to 56 C)
8
th
(87 C to 80 C)
parameter
1
1
0
MTF3 MTF2 MTF1 MTF0 MTE3 MTE2 MTE1 MTE0
(80 C to 72 C)
NOTE: "-" Don't care Description
This command defines temperature gradient compensation coefficient. For this command detail description and opearation, please see Section 1.1.1.
Parameter n MT n 3 MT n 2 MT n 1 MT n 0 Voltage / C (+/- 3mv 0 1 2 3 : : : 12 13 14 15 0 0 0 0 : : : 1 1 1 1 0 0 0 0 : : : 1 1 1 1 0 0 1 1 : : : 0 0 1 1 0 1 0 1 : : : 0 1 0 1 tolerance) 0 mv / C -5 mv / C -10 mv / C -15 mv / C : : : -60 mv / C -65 mv / C -70 mv / C -75 mv / C
o o o o o o o o o
Restriction
Please refer to the specification in absolute maximum ratings for operating voltage range.
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Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value (MTn[3:0])
Default
Status Power On Sequence S/W Reset H/W Reset
1st 2nd 3
rd
parameter 0x50 parameter 0x00 parameter 0x25 parameter 0x61 parameter 0x35 parameter 0x64 parameter 0xAA parameter 0xFF
4th 5
th
6th 7
th
8th Flow Chart
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9.1.73 THYS : Temperature detection threshold(F7H)
Command A0 0 1 /RD 1 1 /WR 0 0 D7 1 D6 1 D5 1 D4 1 D3 0 D2 1 D1 1 D0 1 Hex
(F7h) -
THYS Parameter NOTE: "-" Don't care Description Restriction Register Availability
Status
THYS7 THYS6 THYS5 THYS4 THYS3 THYS2 THYS1 THYS0
Temperature detection threshold setting.
Availability Yes Yes Yes Yes Yes Default Value D[7:0] 06h 06h 06h
Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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9.1.74
Frame Set: Frame PWM Set (F9H)
A0 0 1 1 /RD 1 1 1 /WR 0 0 0 D7 1 D6 1 D5 1 D4 1 P14 P24 D3 1 P13 P23 D2 0 P12 P22 D1 0 P11 P21 D0 1 P10 P20 Hex
(F9h) -
Command
Frame1 Set 1
st
parameter parameter :
:
2nd
:
1 1
:
1 1
:
0 0
:
-
:
-
:
P154 P164
:
P153 P163
:
P152 P162
:
P151 P161
:
P150 P160
15
th
parameter parameter
-
16th
NOTE: "-" Don't care Description Restriction Register Availability
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value Refer to below table. Refer to below table. Refer to below table.
This command is used to set frame1 PWM.
Default
Status Power On Sequence S/W Reset H/W Reset
Flow Chart
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NOTE:
The default value of RGB level set RGB level0 RGB level1 RGB level2 RGB level3 RGB level4 RGB level5 RGB level6 RGB level7 RGB level8 RGB level9 RGB level10 RGB level11 RGB level12 RGB level13 RGB level14 RGB level15 00 08 0A 0D 0F 10 12 14 15 16 17 18 19 1A 1B 1D
All the modulation range of each level for each frame is from 00'H to 1F'H.
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10. SPECIFICATIONS
10.1 ABSOLUTE MAXIMUM RATINGS (VSS = 0V)
Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage range Output voltage range Operating temperature range Storage temperature range
NOTE:
Symbol VDD VDD2, VDD3, VDD4, VDD5 VMAX (V0- XV0) VIN VO TOPR TSTG
Value - 0.3 ~ + 3.0 - 0.3 ~ + 3.6 - 0.3 ~ + 18.0 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 - 30 ~ + 85 - 40 ~ + 125
Unit V V V V V C C
(1). Voltages are all based on VSS = 0V. (2). Voltage relationship: V0VgVmVSSXV0 must always be satisfied.
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DC CHARACTERISTICS
10.2.1 Basic Characteristics
(VSS=0V, Ta = -30 to 85 C)
Parameter Logic Operating voltage Analog Operating voltage Driving voltage input High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Driver on resistance (SEG) Driver on resistance (COM) Frame Rate Symbol VDDI VDDA VLCD VIH VIL VOH VOL IIL RONSEG RONCOM Fr IOH = -1.0mA IOL = +1.0mA VIN = VDD or VSS Vg =3.4, Ta=25 Vg =3.4, Ta=25
Ta = 25 C, N-line=0x06, Duty=70, FR=0x12 NOTE: *1) Applies to IF1, IF2, IF3, /CS, /RST, /WR, /RD, A0(SCL) and D15-D2, D1 (A0) ,D0(SI) pins *2) *3) When the measurements are performed with LCD module, Measurement Points are like below.
Conditions V0 - XV0
Related Pins *2) VDD *2) VDD2,3,4,5 *3) V0, XV0 *1) *2) *1) *2) *2) SI, TE
MIN 1.65 2.4 0.7VDD VSS 0.8VDD VSS
TYP 1.8 2.75 0.5 0.5 77
MAX 3.0 3.3 18.0 VDD 0.3VDD VDD 0.2VDD +1.0 -
Unit V
*1), *2) S0 to S293 C0 to C69
-1.0 -
A
K
Hz
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10.2.2 Current Consumption (Bare die)
Current consumption Operation mode Condition Typical IDD (mA) 1. 1/2 gray pattern 2. Vddi=1.8V, Vdda=2.8V - Normal Mode 3. Vop=12V, bias=1/8, N=0x01, FR=77Hz, x8 booster, Ta=25 0.45 0.68 Maximum IDD (mA)
- Sleep In Mode
Vddi=1.8V, Vdda=2.8V, Ta=25
0.01
0.015
NOTE:
The Current Consumption is DC characteristics of ST7628.
.
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11. TIMING CHARACTERISTICS
11.1 Parallel Interface Characteristics bus (8080-series MCU)
Figure 11.1 Parallel Interface Characteristics bus(8080-series MCU)
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta =25 C)
Signal A0 Symbol TAST TAHT TCHW TCS TRCS TRCSFM TCSF TWC TWRH TWRL TRC TRDH TRDL TRCFM TRDHFM TRDLFM TDST TDHT Parameter Address setup time Address hold time (Write/Read) Chip select "H" pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Write cycle Control pulse "H" duration Control pulse "L" duration Read cycle (ID) Control pulse "H" duration (ID) Control pulse "L" duration (ID) Read cycle (FM) Control pulse "H" duration (FM) Control pulse "L" duration (FM) Data setup time Data hold time MIN 15 15 0 40 100 355 15 250 150 60 250 60 150 550 355 90 35 15 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -
/CS
WR
RD (ID)
When read ID data When read from frame memory
RD (FM) D[15:0]
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Figure 11.2 Rising and Falling timing for Input and Output signal
Figure 11.3 Chip selection (CSX) timing
Figure 11.4 Write to read and Read to write timing
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDD for Input signals.
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11.2 Parallel Interface Characteristics bus (6800-series MCU)
Figure 11.5 Parallel Interface characteristics (6800-Series MCU)
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta =25 C)
Signal A0 Symbol TAST TAHT TCHW TCS TRCS TRCSFM TCSF TCSH TWC TWRH TWRL TRC TRDH TRDL TRCFM TRDHFM TRDLFM TDST TDHT Parameter Address setup time Address hold time (Write/Read) Chip select "H" pulse width Chip select setup time (Write) Chip select setup time (Read ID) Chip select setup time (Read FM) Chip select wait time (Write/Read) Chip select hold time Write cycle Control pulse "H" duration Control pulse "L" duration Read cycle (ID) Control pulse "H" duration (ID) Control pulse "L" duration (ID) Read cycle (FM) Control pulse "H" duration (FM) Control pulse "L" duration (FM) Data setup time Data hold time MIN 15 15 0 40 70 355 10 10 350 100 200 350 100 200 550 90 355 50 15 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -
/CS
R/W
E (ID)
When read ID data When read from frame memory
E (FM) D[15:0]
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11.3 Serial Interface Characteristics (3-pin Serial)
Figure 11.6 3-pin Serial Interface Characteristics
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta =25 C)
Signal /CS Symbol TCHW TCSS TCSH TSCC TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH TACC TOH Parameter /CS "H" pulse width /CS-SCL setup time(Write) /CS-SCL hold time(Write) Chip select setup time Serial clock cycle (Write) SCL "H" pulse width (Write) SCL "L" pulse width (Write) Serial clock cycle (Read) SCL "H" pulse width (Read) SCL "L" pulse width (Read) Data setup time Data hold time Access time Output disable time MIN 45 60 65 20 100 35 35 150 60 60 60 60 10 15 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description
SCL
SI (DIN) (DOUT)
100 50
For maximum CL=30pF For minimum CL=8pF
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11.4 Serial Interface Characteristics (4-pin Serial)
Figure 11.7 4-pin Serial Interface Characteristics
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta =25 C)
Signal /CS Symbol TCSS TCSH TSCC TCHW TSAS TSAH TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH Parameter Chip select setup time Chip select hold time Chip select setup time Chip select setup time Address setup time Address hold time Serial clock cycle (Write) SCL "H" pulse width (Write) SCL "L" pulse width (Write) Serial clock cycle (Read) SCL "H" pulse width (Read) SCL "L" pulse width (Read) Data setup time Data hold time MIN 60 65 20 45 30 30 100 35 35 150 60 60 60 60 MAX Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description
A0
SCL
SI
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12. RESET TIMING
(VSS=0V, VDDI=1.65V to 3.0V, VDDA=2.4V to 3.3V,Ta =25 C)
Rating Item Reset "L" pulse width Signal /RST Symbol tRW Condition Min. 10 -- (*note 5) Reset time tRT 120 -- (*note 6,7) ms Max. -- 5 ms us Units
Notes: 1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from EEPROM (or similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RST 2. Spike due to an electrostatic discharge on RST line does not cause irregular system reset according to the table below: RST Pulse Shorter than 5s Longer than 9s Between 5s and 9s Action Reset Rejected Reset Reset starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out -mode. The display remains the blank state in Sleep In -mode.) and then return to Default condition for Hardware Reset. 4. Spike Rejection also applies during a valid reset pulse as shown below:
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5. When Reset applied during Sleep In Mode. 6. When Reset applied during Sleep Out Mode. 7. It is necessary to wait 5msec after releasing RST before sending commands. Also Sleep Out command cannot be sent for 120msec.
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13. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7628 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7628 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7628 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs
MPU
(2) 6800 Series MPUs
(3) Using the Serial Interface (4-line interface)
MPU
Ver 1.4
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ST7628
MPU
ST7628
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(4) Using the Serial Interface (3-line interface)
MPU
Ver 1.4
ST7628
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A - Application Note A1 - Reference Circuit (3L SPI / COM interlace Mode)
Note1: If VDDI and VDDA need capacitosr toVSS for ripple avoidance, the suggestion type should be 1uf/5V non-polar. Note2: All of the microprocessor interface pin should not be floating on any operations.
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152 COM 5
137 VSS 136 VgIn 135 VgIn
184 COM69 188 SEG0
130 VgIn 129 VgIn 128 VgS 127 VgOut 126 VgOut 125 XV0In 124 XV0In 123 XV0In 122 XV0In 121 XV0S 120 XV0Out 119 XV0Out 118 V0Out 117 V0Out 116 V0S 115 V0In 114 V0In 113 V0In 112 V0In 111 VREF 110 Vm 109 VDD2
100 VDD2 99 VDD5 98 VDD5 97 VDD5 96 VDD5 95 VDD5 94 VDD5 93 VDD5 92 VDD5 91 VDD4 90 VDD4 89 VDD3 88 VDD3 87 VSS4 86 VSS4 85 VSS2 84 VSS2 83 VSS2 82 VSS2
X
Y
(0,0)
76 VSS2 75 VSS2 74 VSS2 73 VSS 72 VSS 71 VSS 70 VSS 69 VSS1 68 VSS1 67 VDD 66 VDD 65 VDD 64 VDD 63 VDD 62 VDD 61 TCAP 60 TE 59 /EXT 58 /CS 57 VDD 56 VSS 55 IF3 54 IF2 53 IF1 52 CSEL 51 RST 50 E_RD 49 VDD 48 VSS 47 D15 46 D14 45 D13 44 D12 43 D11 42 D10 41 D9
481 SEG293 485 COM68
40 D8 39 D7 38 D6 37 D5 36 D4 35 D3 34 D2 33 D1 32 D0 31 RW_WR 30 A0 29 VDD 28 CLS 27 CL 26 VPP 25 VPP 24 VPP 23 VPP 22 VSS 21 dummy
517 COM4
15 dummy
Ver 1.4
ST7628
A1 - Reference Circuit (4L SPI / COM interlace Mode)
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152 COM 5
137 VSS 136 VgIn 135 VgIn
184 COM69 188 SEG0
130 VgIn 129 VgIn 128 VgS 127 VgOut 126 VgOut 125 XV0In 124 XV0In 123 XV0In 122 XV0In 121 XV0S 120 XV0Out 119 XV0Out 118 V0Out 117 V0Out 116 V0S 115 V0In 114 V0In 113 V0In 112 V0In 111 VREF 110 Vm 109 VDD2
100 VDD2 99 VDD5 98 VDD5 97 VDD5 96 VDD5 95 VDD5 94 VDD5 93 VDD5 92 VDD5 91 VDD4 90 VDD4 89 VDD3 88 VDD3 87 VSS4 86 VSS4 85 VSS2 84 VSS2 83 VSS2 82 VSS2
X
Y
(0,0)
76 VSS2 75 VSS2 74 VSS2 73 VSS 72 VSS 71 VSS 70 VSS 69 VSS1 68 VSS1 67 VDD 66 VDD 65 VDD 64 VDD 63 VDD 62 VDD 61 TCAP 60 TE 59 /EXT 58 /CS 57 VDD 56 VSS 55 IF3 54 IF2 53 IF1 52 CSEL 51 RST 50 E_RD 49 VDD 48 VSS 47 D15 46 D14 45 D13 44 D12 43 D11 42 D10 41 D9
481 SEG293 485 COM68
40 D8 39 D7 38 D6 37 D5 36 D4 35 D3 34 D2 33 D1 32 D0 31 RW_WR 30 A0 29 VDD 28 CLS 27 CL 26 VPP 25 VPP 24 VPP 23 VPP 22 VSS 21 dummy
517 COM4
15 dummy
Ver 1.4
ST7628
A1 - Reference Circuit (80-8bits / COM interlace Mode)
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152 COM 5
137 VSS 136 VgIn 135 VgIn
184 COM69 188 SEG0
130 VgIn 129 VgIn 128 VgS 127 VgOut 126 VgOut 125 XV0In 124 XV0In 123 XV0In 122 XV0In 121 XV0S 120 XV0Out 119 XV0Out 118 V0Out 117 V0Out 116 V0S 115 V0In 114 V0In 113 V0In 112 V0In 111 VREF 110 Vm 109 VDD2
100 VDD2 99 VDD5 98 VDD5 97 VDD5 96 VDD5 95 VDD5 94 VDD5 93 VDD5 92 VDD5 91 VDD4 90 VDD4 89 VDD3 88 VDD3 87 VSS4 86 VSS4 85 VSS2 84 VSS2 83 VSS2 82 VSS2
X
Y
(0,0)
76 VSS2 75 VSS2 74 VSS2 73 VSS 72 VSS 71 VSS 70 VSS 69 VSS1 68 VSS1 67 VDD 66 VDD 65 VDD 64 VDD 63 VDD 62 VDD 61 TCAP 60 TE 59 /EXT 58 /CS 57 VDD 56 VSS 55 IF3 54 IF2 53 IF1 52 CSEL 51 RST 50 E_RD 49 VDD 48 VSS 47 D15 46 D14 45 D13 44 D12 43 D11 42 D10 41 D9
481 SEG293 485 COM68
40 D8 39 D7 38 D6 37 D5 36 D4 35 D3 34 D2 33 D1 32 D0 31 RW_WR 30 A0 29 VDD 28 CLS 27 CL 26 VPP 25 VPP 24 VPP 23 VPP 22 VSS 21 dummy
517 COM4
15 dummy
Ver 1.4
ST7628
A1 - Reference Circuit (68-8bits / COM interlace Mode)
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A2 - Power On
Power On Keeping the /RES Pin = "L" and waiting for stabilizing the Power /RES Pin="H" and wait tRT ( tRT > 120 ms )
trTW
trTW= >0
VDDI
(Digital)
VDDA
(Analog)
/RES t RW Internal State Power On Reset
tRW > 10 us
Normal Sate
trTW
trTW>0
VDDI
(Digital)
VDDA
(Analog)
/RES t Internal State Power On
RW
t RW > 10 us
Normal Sate
Reset
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A3 - Power off
Normal State
Sleep In
1. 2.
OSC OFF Power System OFF (Booster OFF)
Keeping /RES Pin ="L"
Power Off (tRT>120ms)
End of Power OFF tfPW tfPW>0
VDDI
(Digital)
VDDA
(Analog)
/RES
t RT Internal State Normal State Reset
tR T >
120 ms
Power Off
Keep the /RES = Low
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A4 - Sleep In Flow
1. OSC OFF 2. Power System OFF (Booster OFF)
A5 - Sleep Out Flow
1. OSC ON 2. Power System ON (Booster ON)
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A6 - OTP Burning Flow:
Ver 1.4
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A7 - Software coding flow
void Initial_LCD_Module(void) {
//-----------disable autoread + Manual read once ------------------------------Write(COMMAND,0xd7); Write(DATA,0xdf); Write(COMMAND,0xE0); Write(DATA,0x00); delayms(10); Write(COMMAND,0xE3); delayms(20); Write(COMMAND,0xE1); // Auto Load Set // Auto Load Disable // EE Read/write mode // Set read mode // Delay 10ms // Read active // Delay 20ms // Cancel control
//---------------------------------- Sleep OUT --------------------------------------------Write(COMMAND, 0x11 ); delayms(50); // Sleep Out //Delay 50ms
//--------------------------------Vop setting-----------------------------------------------Write(COMMAND,0xC0); Write(DATA, 0xD2); Write(DATA, 0x00); //Set Vop by initial Module //Vop = 12V //Base Vop voltage
//----------------------------Set
Write(COMMAND,0xC3); Write(DATA,0x02); Write(COMMAND,0xC4); Write(DATA,0x07); Write(COMMAND,0xC5); Write(DATA,0x21); Write(COMMAND,0xCB); Write(DATA,0x01);
Register-----------------------------------------// Bias select // Setting Booster times // Booster efficiency // BE = 0x01 (Level 2) // Vg with booster x2 control // Vg from Vdd2 // ID1 = 00 // // ID3 = 00 // Analog circuit setting //
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Write(COMMAND,0xCC); Write(DATA,0x00); Write(COMMAND,0xCE); Write(DATA,0x00); Write(COMMAND,0xD0); Write(DATA,0x1D);
Ver 1.4
ST7628
Write(COMMAND,0x3A); Write(DATA,0x05); Write(COMMAND,0x36); Write(DATA,0x00); Write(COMMAND,0xF7 ); Write(DATA,0x06); Write(COMMAND, 0xB5 ); Write(DATA, 0x01); // command for temp sensitivity. // // N-Line // RST, 2-line inversion // Color mode = 65k // // Memory Access Control //
1. Set Gamma table for Module, please refer spec setting. 2. Set Temp compensation for Module, please refer spec setting. Write(COMMAND,0x2A); Write(DATA,0x00); Write(DATA,0x61); Write(COMMAND,0x2B); Write(DATA,0x00); Write(DATA,0x45); } void Set_OTP_Register(void) { // COL// // Start address = 0 // End address = 97 // ROW // // Start address = 0 // End address = 69
//--------------------------------Set OTP register----------------------------------------
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Write(COMMAND, 0xCD ); Write(DATA, 0x80 ); Write(COMMAND, 0xB5 ); Write(DATA, 0x01); Write(COMMAND,0xD0); Write(DATA,0x1D); Write(COMMAND,0xD7); Write(DATA,0x9F); Write(COMMAND,0xB4); Write(DATA,0x18); } void Fine_Tune_Vop(void) { // N-Line // RST, 2-line inversion // Analog circuit setting // //Auto read Set //OTPB Disable //PTL Mode Select //PTLMOD Normal Mode //ID2
//------------------------------------- Show Map ----------------------------------------------Show_Image(); Write(COMMAND, 0x29 ); Write( COMMAND, 0xC1); or Write( COMMAND, 0xC2);
Note
//Display a image // Display On //Fine tuning Vop here by command 0xc1(VopOffsetInc),0xc2(VopOffsetDec).
//------------------------------------ Display ON ----------------------------------------------//--------------------------------Fine tune Vop offset----------------------------------------
} void OTP_Writing(void) {
//--------------------------------Display OFF---------------------------------------Write(COMMAND, 0x28 ); Delayms(50); Write( COMMAND, 0x00F0 ); Write( DATA, 0x0012 ); Write( DATA, 0x0012 );
Ver 1.4 2008/08
// Display Off // delay 50ms // Keep Frame Rate with 77Hz
//--------------------------------OTP writing----------------------------------------
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Write( DATA, 0x0012 ); Write( DATA, 0x0012 ); Write( COMMAND, 0x00E4 ); Write( DATA, 0x0058 ); Write( COMMAND, 0x00E5 ); Write( DATA, 0x0009 ); Write( COMMAND, 0x00E0 ); Write( DATA, 0x0020 ); Delayms(100); Write( COMMAND, 0x00E2 ); Delayms(100); Write( COMMAND, 0x00E1 ); Write(COMMAND, 0x10 ); } // Read/write mode setting // Set Write mode // Delay 100ms // Write active // Delay 100ms // Cancel control // Sleep In //OTP selection // Select OTP // Set OTP writing setup
Note:
In this section"+" & "-" key button, please execute Write(COMMAND,0xC1) to increase one step at Vop and execute Write(COMMAND,0xC2) to decrease one step at Vop, if necessary.
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Modification History
Version 0.X 1.0 1.1 1.2 1.3 2007/2/7 2007/2/27 2007/3/1 2007/6/12 Date Preliminary version. First issue. Modify command table list and descriptions. Add command 0x2E for memory reading. 1. Redefine the programming mechanism of non-volatility memory. 2. Modify 6800 and 3-pin Serial timing 1. Delete the P/SX pin. 2. Fixed TFA and BFA area. 3. Fixed the default value typos. 4. Fixed default value 5. Fixed the flow chart 1.4 2008/08 6. Add the symbol on Figure11.6 for reading condition and Tscc. 7. Fixed the table format. 8. Fixed the direction of reset and SI signal. 9. Modify Current Consumption table 10. Remove external clock function 11. Modify AC/DC characteristics Description
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